Abstract: An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the pre-biased output. After the high side switch is activated, a low side switch is activated to draw a second current from the pre-biased output such that the magnitude of the first current is greater than the magnitude of the second current for at least a portion of a time period T1. After the time period T1 ends, the magnitudes of the first and second currents are changed to maintain a predetermined voltage on the pre-biased output.

Abstract: An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the pre-biased output. After the high side switch is activated, a low side switch is activated to draw a second current from the pre-biased output such that the magnitude of the first current is greater than the magnitude of the second current for at least a portion of a time period T1. After the time period T1 ends, the magnitudes of the first and second currents are changed to maintain a predetermined voltage on the pre-biased output.

Abstract: A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference voltages are measured for at least two different trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured reference voltages. A trim setting associated with the reference voltage circuitry of the given die is set according to the modified target reference voltage so as to compensate for an offset voltage and substantially achieve the desired target reference voltage.

Abstract: A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference voltages are measured for at least two different trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured reference voltages. A trim setting associated with the reference voltage circuitry of the given die is set according to the modified target reference voltage so as to compensate for an offset voltage and substantially achieve the desired target reference voltage.

Abstract: A capacitively compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port, including a compensation capacitor having a plate connected to a node internal to the voltage regulator, and including a current source coupled between the voltage supply and the internal node. The voltage regulator also includes a low power control circuit responsive to a low power command signal.

Abstract: A capacitively compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port, including a compensation capacitor having a plate connected to a node internal to the voltage regulator, and including a current source coupled between the voltage supply and the internal node. The voltage regulator also includes a low power control circuit responsive to a low power command signal.

Abstract: An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank.

Abstract: In one aspect, the present invention provides a method of generating a substantially constant voltage. A bandgap reference circuit (112/114/116) is trimmed such that a voltage output (VBG) from the bandgap reference circuit is at its peak value when an operating temperature is at its minimum value within a specified operating temperature range. A plurality of additional current sources (118-124) are also provided with the bandgap reference circuit. Each current source is designed to successively provide additional current as the operating temperature increases within the specified operating temperature range.

Abstract: An integrated circuit (12) made with a CMOS P-epi process includes a bandgap circuit (16). A pair of PNP bipolar junction transistors (73, 72) have respective currents flowing through them with a ratio of 8 to 1. A differential stage has a further pair of PNP bipolar junction transistors (66, 67) which are identical, and which have their emitters coupled to each other and to a power source (11). Each transistor of the further pair has a base coupled to the emitter of a respective transistor of the first pair. The output of the differential stage controls a current source (82), which causes a current to flow through multiple resistors (86, 87, 88) and through a diode (30). One of the resistors (87) has its ends coupled to the respective bases of the transistors of the first pair.

Abstract: A charge pump uses switching transistors including a PMOS transistor (P1), a first transistor (N1), and a second transistor (N2) instead of diodes (D1, D2) to control the transfer of charge from a pump capacitor (14) to a storage capacitor (20). The voltage (60) at the storage capacitor (20) is applied to a level shifter (13) and to the source of the PMOS transistor (P1) which, in turn, biases the first transistor (N1) during low state of an oscillating waveform (30B). A supply rail (140) charges the pump capacitor (14) when the first transistor (N1) is in its active region during the low state of the oscillating waveform (30B) and turns OFF during the high state of the waveform (30B) causing the charge on the pump capacitor (14) to be transferred to the storage capacitor (20). The level shifter (13) is used to synchronize the oscillating waveform (30B) so that no charge is lost from the pump capacitor (14) back to the supply and minimal charge is conducted through a parasitic diode (55).

Abstract: An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank.

Abstract: A circuit (10) is disclosed for enabling voltage to be sensed across a power transistor (12) of the type which has first and second active regions, such as source (85) and drain (76) regions of an MOS transistor (12), or emitter and collector regions of a bipolar transistor (42), in a semiconductor substrate (72), with the first region (76) located along a first lateral extent in the substrate (72) to have ends at terminal locations (D1,S1) of the first lateral extent and the second region located along a second lateral extent in the substrate (72) to have ends at terminal locations (D2,S2) of the second lateral extent. The circuit (10) includes a first conductive line (20) connected to the first region at said terminal locations (D1,D2) of the first lateral extent, and a first voltage sensing connection (22) to a midpoint of the first conductive line (20).

Abstract: An integrated circuit and method for using same is constructed on a semiconductor substrate (15) with a structure (24) in the substrate (15) having an electrical value desired to be trimable and with a conducting layer (33) on the substrate (15) insulated (30) from the structure (14) except at one location (26), which is electrically connected to a first part of the structure (24). An oxide layer (48) separates one portion of the structure (24) from a part of the conductor (33). The second oxide layer (48) has a predetermined breakdown voltage such that when a voltage, V.sub.TRIM, larger than the second predetermined breakdown voltage is applied between the conductor (33) and the structure (24), the second oxide layer (48) breaks down, shorting the first and second parts (46, 50) of the structure (24) to trim its value.

Abstract: A low voltage drop out circuit (10) has a voltage regulating transistor (13) between a supply voltage (12) and an output terminal (28). An active feedback loop controls the voltage regulating transistor (13) according to a magnitude of the supply voltage (12) to control the voltage on the output terminal (28). A reference voltage source (25) produces a reference voltage, and a switch, which may be a second transistor (45) of similar type than the voltage regulating transistor (13), is connected in parallel with the voltage regulating transistor (13). A comparing circuit (42) detects when the supply voltage (12) falls below the reference voltage (25) to operate the second transistor (45), which may be sized to be much larger than the voltage regulating transistor (13) to effectively short across the voltage regulating transistor (13) when the supply voltage (12) falls below a predetermined level.

Abstract: The voltage regulator circuit contains a MOS transistor 12 connected between a voltage supply line 22 and an output line 30. The MOS transistor 12 provides a stable voltage on the output line 30 independent of voltage transients on the voltage supply line 22 and independent of current transients on the output line 30. An amplifier 14 coupled to the MOS transistor 12 controls the response of the MOS transistor 12. Feedback circuitry connected between the output line 30 and the amplifier 14 provides feedback to the amplifier 14. A voltage source 16 provides the reference for amplifier 14.

Abstract: A bandgap reference circuit (14) in a bandgap voltage reference device (10) generates a bandgap voltage reference (V.sub.BG) at the base of a Q1 transistor (22) and a Q2 transistor (20). A reference current signal I.sub.T flows into the collectors of the Q2 transistor (20) and the Q1 transistor (22) as generated by a difference in base to emitter voltages due to a difference in emitter areas between the Q2 transistor (20) and the Q1 transistor (22). A correction current signal (I.sub.TT) generated by a current squaring circuit (16) is injected into the collector of the Q1 transistor (22) such that the collectors of the Q2 transistor (20) and the Q1 transistor (22) have unequal current values. The current squaring circuitry (16) generates the correction current signal (I.sub.TT) by squaring the reference current signal (I.sub.T) and dividing it into a sampling current signal (I.sub.SC ) generated in a current generator amplifier (18).

Abstract: A voltage reference circuit (2) is provided which includes a 2nd order curvature correction circuit (3) that eliminates undesirable 2nd order polynomial temperature dependency characteristics. A bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) forms a bandgap current (I.sub.X) that is dependent upon absolute temperature. A translinear cell (Q15, Q14, Q13, Q12, Q11 and Q10) transforms this current in a squaring transformation and divides the squared current by a temperature independent current (I.sub.X). A current mirror (Q17 and Q16) adjusts the value of the squared current so that it approximates the value of the 2nd order term of the bandgap reference circuit.

Abstract: A current switch (30) includes a switching transistor (Q1) having a collector electrode for coupling to a first voltage source (Vcc), an emitter electrode, and a base electrode for receiving a control signal (V.sub.IN1). Switching transistor (Q1) is responsive to the control signal (V.sub.IN1) to turn on to produce a collector current (I.sub.CQ1). A bias circuit (26) is coupled to the emitter electrode of the switching transistor (Q1) for causing the collector current (I.sub.CQ1) of the switching transistor (Q1) to have a predetermined value. The bias circuit includes first and second transistors (Q3 and Q4) having base electrodes coupled in common. The first transistor (Q3) has a collector electrode coupled to the emitter electrode of the switching transistor (Q1) and an emitter electrode for coupling to a second voltage source (Vss). The second transistor has a collector electrode for coupling to a current source (24) and an emitter electrode for coupling to the second voltage source (Vss).