Abstract: Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

Abstract: Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

Abstract: A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

Abstract: A down-converter and a testing device for the down-converter are provided. The down-converter implements a Class-AB single-end input, differential output double balanced mixer structure. By introducing an on-chip bias loop, it significantly improves the symmetry and linearity of the mixer. The down-converter on-chip implements an input impedance match circuit and an open-drain output stage. By optimizing the circuit structure and each device, it achieves the objectives of a high conversion gain, high linearity, and low noise coefficient.

Abstract: A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

Abstract: A down-converter and a testing device for the down-converter are provided. The down-converter implements a Class-AB single-end input, differential output double balanced mixer structure. By introducing an on-chip bias loop, it significantly improves the symmetry and linearity of the mixer. The down-converter on-chip implements an input impedance match circuit and an open-drain output stage. By optimizing the circuit structure and each device, it achieves the objectives of a high conversion gain, high linearity, and low noise coefficient.

Abstract: A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

Abstract: A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

Abstract: A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.