Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.

Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating dielectric stack comprising a plurality of dielectric layer pairs arranged in a vertical direction; n alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs arranged in the vertical direction; and at least one through array contact extending through the alternating dielectric stack in the vertical direction; a barrier structure separates the alternating dielectric stack and the alternating conductor/dielectric stack, an opening of the barrier structure is at an edge of the alternating dielectric stack along a lateral direction, the lateral direction is perpendicular to the vertical direction.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.