Abstract: Certain aspects of the present disclosure generally relate to optimizing, or at least reducing, power consumption and/or hold timing issues within an integrated circuit (IC). One example IC generally includes a global power supply rail and a first power block. The first power block includes a first plurality of head switch cells coupled to the global power supply rail. Each head switch cell includes a head switch coupled between the global power supply rail and a power node for the head switch cell. The first plurality of head switch cells is configured such that a first set of the first plurality of head switch cells can be programmed on and a second set of the first plurality of head switch cells can be programmed off.