Abstract: An IC is provided. The IC includes a power grid including Mx layer interconnects extending in a first direction on an Mx layer and Mx+1 layer interconnects extending in a second direction orthogonal to the first direction on an Mx+1 layer, where x>5. In addition, the IC includes a plurality of power switches. Further, the IC includes at least one sensing element located between the Mx layer and the Mx+1 layer and configured to measure a voltage drop to devices powered by the plurality of power switches. The one or more of the plurality of power switches may be located below the power grid. The power switches of the plurality of power switches may be adjacent in the first direction and in the second direction to each sensing element of the at least one sensing element.

Abstract: A clock generation circuit has an injection-locked oscillator, a frequency doubler circuit, low pass filters and a calibration circuit. The injection-locked oscillator has an input coupled to a half-rate clock signal. The frequency doubler circuit has inputs coupled to outputs of the injection-locked oscillator. Each of the low pass filters has an input coupled to one of a plurality of outputs of the frequency doubler circuit. The calibration circuit includes comparison logic that receives outputs of the low pass filters. The calibration circuit has an output coupled to a control input of a source of a supply current in the injection-locked oscillator. In one example, the source of the supply current is a current digital to analog converter.

Abstract: A method and an apparatus to provide bandgap calibration for multiple outputs are disclosed. In one implementation, a computing chip includes a bandgap current generator; a first adjustable current output coupled to the bandgap current generator; a second adjustable current output coupled to the bandgap current generator; a first switch selectively coupling the first adjustable current output to a calibration circuit and to a first analog-to-digital converter (ADC); and a second switch selectively coupling the second adjustable current output to a load on the computing chip and to the ADC.

Abstract: An IC is provided. The IC includes a power grid including Mx layer interconnects extending in a first direction on an Mx layer and Mx+1 layer interconnects extending in a second direction orthogonal to the first direction on an Mx+1 layer, where x>5. In addition, the IC includes a plurality of power switches. Further, the IC includes at least one sensing element located between the Mx layer and the Mx+1 layer and configured to measure a voltage drop to devices powered by the plurality of power switches. The one or more of the plurality of power switches may be located below the power grid. The power switches of the plurality of power switches may be adjacent in the first direction and in the second direction to each sensing element of the at least one sensing element.

Abstract: A method and an apparatus to provide bandgap calibration for multiple outputs are disclosed. In one implementation, a computing chip includes a bandgap current generator; a first adjustable current output coupled to the bandgap current generator; a second adjustable current output coupled to the bandgap current generator; a first switch selectively coupling the first adjustable current output to a calibration circuit and to a first analog-to-digital converter (ADC); and a second switch selectively coupling the second adjustable current output to a load on the computing chip and to the ADC.

Abstract: A system includes a bandgap voltage generator coupled to a voltage supply and configured to produce a plurality of reference voltage levels in response to a plurality of calibration codes; an analog-to-digital converter (ADC) coupled to a reference voltage output of the bandgap voltage generator; a logic circuit coupled to an output of the ADC; a first memory element coupled to the logic circuit and configured to store a calibration coefficient indicative of a relationship of the calibration codes and the reference voltage levels; and a second memory element coupled to the logic circuit and configured to store a value of a first reference voltage level for the reference voltage output, wherein the logic circuit is configured to generate a first calibration code from the value of the first reference voltage level and the calibration coefficient.

Abstract: A device for reducing a self-interference contribution in a full-duplex wireless communication system configured to transmit a transmission signal and modulated by a baseband signal, and configured to receive a reception signal containing a self-interference contribution corresponding to the transmission signal, the reduction device comprising a first reduction module, configured to take a replica of the transmission signal, and configured to generate a first reduction signal, the device further comprising: a second reduction module, arranged so as to be able to take a replica of the baseband signal, and capable of generating a second reduction signal that is a function of the temporal derivative of the baseband signal, a subtractor, linked to the first reduction module and to the second reduction module, and configured to subtract from the reception signal the first reduction signal and the second reduction signal.

Abstract: A device for reducing a self-interference contribution in a full-duplex wireless communication system configured to transmit a transmission signal and modulated by a baseband signal, and configured to receive a reception signal containing a self-interference contribution corresponding to the transmission signal, the reduction device comprising a first reduction module, configured to take a replica of the transmission signal, and configured to generate a first reduction signal, the device further comprising: a second reduction module, arranged so as to be able to take a replica of the baseband signal, and capable of generating a second reduction signal that is a function of the temporal derivative of the baseband signal, a subtractor, linked to the first reduction module and to the second reduction module, and configured to subtract from the reception signal the first reduction signal and the second reduction signal.