Abstract: A charging discharging apparatus is applied to two super capacitor modules. The charging discharging apparatus includes a control unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first charging switch unit, a second charging switch unit and a charging unit. When an input power apparatus sends an input power to the charging discharging apparatus, the charging discharging apparatus enters a charging mode, so that the super capacitor module having the lower voltage is charged until the voltages of the two super capacitor modules are equal, and then the two super capacitor modules are charged simultaneously in parallel. When the input power apparatus stops sending the input power to the charging discharging apparatus, the two super capacitor modules discharge in series.

Abstract: A charging discharging apparatus includes a control unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit and a fifth switch unit. When an input power apparatus sends an input power to the charging discharging apparatus, the control unit turns off the second switch unit and the fourth switch unit, and the control unit turns on the first switch unit, the third switch unit and the fifth switch unit, so that a power load apparatus receives the input power through the first switch unit, and the first super capacitor module is connected to the second super capacitor module in parallel, and the first super capacitor module and the second super capacitor module are charged.

Abstract: A charging discharging apparatus is applied to two super capacitor modules. The charging discharging apparatus includes a control unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first charging switch unit, a second charging switch unit and a charging unit. When an input power apparatus sends an input power to the charging discharging apparatus, the charging discharging apparatus enters a charging mode, so that the super capacitor module having the lower voltage is charged until the voltages of the two super capacitor modules are equal, and then the two super capacitor modules are charged simultaneously in parallel. When the input power apparatus stops sending the input power to the charging discharging apparatus, the two super capacitor modules discharge in series.

Abstract: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention would reduce the data read/write time and increase the life-span of flash memory.

Abstract: A method for page random write and read in blocks of flash memory is disclosed. The data could be random written in the pages of block. The pages would be arranged when the block was filled with data, so as to prevent from data copied and erased repeatedly. Present invention would reduce the data read/write time and increase the life-span of flash memory.

Abstract: The present invention provides an easy access ports structure. In accordance with the present invention, each port has a register bank. Each register bank has the same address. A global register is used in the present invention to store the status values. When operating, the CPU accesses one port in accordance with the application program. The status values of the other ports are mapped to the global register. Therefore, the CPU also can understand the other ports status through the global register when accessing one port.

Abstract: A control system and method for the CCD scanner, wherein the CCD can process multiple primary colors and includes a shift register and a transfer gate. The control system at least includes a transfer controller. The characteristic includes providing a transfer signal and multiple charge-shift clock signals, wherein any each one charge-shift clock signal corresponds to one primary color. All charge data with respect to the primary colors are transferred to the shift register through the transfer gate in once operation when the transfer signal is true. The shift register shifts out the charge data according to each of the charge-shift clock signals charge coupled device.

Abstract: A method for reading an automatically adaptive memory card and a memory card controller are provided. First, whether a present reading address of a reading command is the same as a previous reading address is determined. Next, when the present reading address is determined to be the same as the previous reading address, a response is output and a data is output in a data-lag mode to output the data after the response is outputted. On the other hand, when the present reading address is not the same as the previous reading address, the previous reading address is updated to be the present reading address, the response is output and the data is output in a data-parallel mode to output the data regardless of whether or not the response is outputted. Hence, the memory card with the invention is compatible with several card readers on the market.

Abstract: A method for reading an automatically adaptive memory card and a memory card controller are provided. First, whether a present reading address of a reading command is the same as a previous reading address is determined. Next, when the present reading address is determined to be the same as the previous reading address, a response is output and a data is output in a data-lag mode to output the data after the response is outputted. On the other hand, when the present reading address is not the same as the previous reading address, the previous reading address is updated to be the present reading address, the response is output and the data is output in a data-parallel mode to output the data regardless of whether or not the response is outputted. Hence, the memory card with the invention is compatible with several card readers on the market.

Abstract: A device capable of indicating access modes for an accessible memory card comprises an indicator and an interface electrically connected to a controller of the accessible memory card and to the indicator. The indicator is driven by the interface to show users that the accessible memory card is performing an access operation when the controller gives commands to the accessible memory card.

Abstract: The present invention provides an easy access ports structure. In accordance with the present invention, each port has a register bank. Each register bank has the same address. A global register is used in the present invention to store the status values. When operating, the CPU accesses one port in accordance with the application program. The status values of the other ports are mapped to the global register. Therefore, the CPU also can understand the other ports status through the global register when accessing one port.

Abstract: The present invention proposes an output signal circuit capable of automatically detecting polarity, whose input/output signal terminal of the output signal circuit has both input and output functions. When a system undergoes a power on reset or a hardware reset, the output signal circuit can be shut off, and the input state of the input/output signal terminal is used to set the polarity of output signal. After reset, the pin is restored to its normal output. When an IC has the output signal capable of automatically detecting polarity, the flexibility in design of application circuits can be enhanced. Limitation of usage of IC due to fixed polarity of output signal can thus be avoided.

Abstract: The present invention proposes an apparatus and method for reading the default value of a peripheral component to resolve the drawbacks of in expansibility, inconvenience in installation and higher manufacturing cost in the prior art. In order to accomplish the objective, the default value of the peripheral component is set up by a circuit board where the peripheral component situated, or stored inside a memory means in the present invention. When the system starts, the peripheral component reads the setup of the circuit board first. If there is no default value set up by the circuit board, the memory will be read. Next, the peripheral component will be set up according to the default value. Finally, the memory will be disabled to save power consumption.

Abstract: The present invention proposes an output signal circuit capable of automatically detecting polarity, whose input/output signal terminal of the output signal circuit has both input and output functions. When a system undergoes a power on reset or a hardware reset, the output signal circuit can be shut off, and the input state of the input/output signal terminal is used to set the polarity of output signal. After reset, the pin is restored to its normal output. When an IC has the output signal capable of automatically detecting polarity, the flexibility in design of application circuits can be enhanced. Limitation of usage of IC due to fixed polarity of output signal can thus be avoided.

Abstract: A telephone signal detecting circuit is provided, which can identify an input signal is a line reversal signal or a ring signal. Providing this telephone signal detecting circuit into a ring detector of a conventional telephone set can share the burden of the microprocessor of the telephone set and lessen the loading of power supply. In this invention, the Schmitt triggers of two different trigger levels are used to respectively detect the voltage change of the first discharge of the capacitor and the ripple signal produced due to the charge of the capacitor by the ring signal. The input signal can be easily identified to be a line reversal signal or a ring signal through a simple flip-flop circuit that can reduce the influence of the bouncing effect. The telephone signal detecting circuit is operated in a static mode and is almost free of power-consumption when it is not working.

Abstract: A telephone set device capable of vocalizing a telephone number being called. A line interface circuit serves as an interface between the tip and ring wires of a standard telephone circuit and the internal circuit. A ring detector detects whether a ring signal is being input. A controller provides the input of signals from the line interface circuit, the keypad, and the ring detector. A hybrid circuit divides the connecting terminals of the line interface into a voice input and a voice output. A keypad inputs the control signal or the number signal to the controller, and sets the address data in the internal memory of the controller to output the voice data. A DTMF generator generates DTMF signals to represent each key on the keypad. A number voice generator receives the address data and decompresses the corresponding compressed voice data retrieved from the internal memory. A handset receives/transmits a voice signal.

Abstract: A microcomputer system and method of utilizing a repeated reset operation to enter the microcomputer system into different operating modes, particularly a microcomputer system without a keyboard, in which only a reset key is needed to set the required operating mode. The microcomputer system of the present invention comprises: a microcomputer; a memory connected to the microcomputer; a reset key to reset the microcomputer system; and a reset circuit to provide a power on reset pulse required in the microcomputer system or to receive the reset pulse produced by reset key. The microcomputer system checks both a specific memory area content for only a first specific value and a dedicated address content in the memory for a second specific value. If both only the first specific value in specific memory area and the second specific value in dedicated address are present, the microcomputer system is set to an abnormal operating mode. Otherwise, the specific value is written into the dedicated address in the memory.

Abstract: A compression circuit for quick compression processing of two-dimensional image data, using a simple hardware configuration and operation to deal with the scanned two-dimensional image data quickly, and increasing the data compression ratio. Such a compression configuration for quickly processing two-dimensional image data mainly depends on the fact that the strong correlation between the upper pixel and previous pixel of the currently scanned pixel. By computing the difference between the scanned pixel and the previous and upper pixel, respectively, and using the conventional encoding method, a higher compression ratio is achieved, thereby reducing the processing time for the data compression.

Abstract: A control system and method for the CCD scanner, wherein the CCD can process multiple primary colors and includes a shift register and a transfer gate. The control system at least includes a transfer controller. The characteristic includes providing a transfer signal and multiple charge-shift clock signals, wherein any each one charge-shift clock signal corresponds to one primary color. All charge data with respect to the primary colors are transferred to the shift register through the transfer gate in once operation when the transfer signal is true. The shift register shifts out the charge data according to each of the charge-shift clock signals.

Abstract: The present invention discloses a power-on circuit of a peripheral component, which comprises a switch control circuit for controlling the enabling time of a P-type or N-type transistor. For a P-type transistor, the switch control circuit includes a pull-high element, a current source and a current switch. For a N-type transistor, the switch control circuit includes a pull-down element, a current source and a current switch. The enabling time of the P-type or N-type transistors are controlled by the switch control circuit and the capacitor shunt with the switch control circuit so as to slowly enable the transistor switch. In other words, the present invention uses the slowly increasing or decreasing characteristic caused by charging the capacitor with the current source to control the P-type or N-type transistor switch so as to obtain the purpose of slowly enabling the power supply.