Patents by Inventor Bar Shapira
Bar Shapira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12294469Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.Type: GrantFiled: August 11, 2022Date of Patent: May 6, 2025Assignee: Mellanox Technologies, LtdInventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20240373379Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.Type: ApplicationFiled: July 24, 2023Publication date: November 7, 2024Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Liron Mula, Ariel Almog, Bar Shapira, Guy Lederman
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Patent number: 12028155Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.Type: GrantFiled: November 24, 2021Date of Patent: July 2, 2024Assignee: Mellanox Technologies, LTD.Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen, Liron Mula
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Publication number: 20240204897Abstract: In one embodiment, a processing system includes an interface controller to receive a data signal from a remote link partner over a link, and recover a clock signal from the received data signal, frequency generation circuitry to receive the recovered clock signal, and output a local clock signal responsively to the received recovered clock signal, wherein the interface controller is configured to drive a transmit symbol rate responsively to the local clock signal, and a digital control loop including the interface controller and the frequency generation circuitry, wherein the interface controller is configured to identify a clock drift, generate a digital control signal responsively to the clock drift, and send the digital control signal to the frequency generation circuitry, which is configured to adjust a frequency of the local clock signal responsively to the digital control signal in order to reduce the clock drift.Type: ApplicationFiled: December 19, 2022Publication date: June 20, 2024Inventors: Natan Manevich, Dotan David Levi, Maciek Machnikowski, Wojciech Wasko, Bar Shapira, Jonathan Oliel, Ofir Sadeh
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Publication number: 20240154712Abstract: A system for maintaining a Precision Time Protocol (PTP) hardware clock, the system being operative in conjunction with a network device which is external to the system, the system comprising a controller to receive information characterizing a network peer oscillator frequency, wherein the information was extracted from an RX symbol rate, and to adjust the PTP Hardware Clock's frequency responsive to the information characterizing the network peer oscillator frequency.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen, Liron Mula
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Patent number: 11853116Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.Type: GrantFiled: January 24, 2022Date of Patent: December 26, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Natan Manevich, Bar Shapira
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Patent number: 11835999Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.Type: GrantFiled: January 18, 2022Date of Patent: December 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen
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Publication number: 20230367358Abstract: In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.Type: ApplicationFiled: July 19, 2022Publication date: November 16, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20230370305Abstract: In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.Type: ApplicationFiled: August 11, 2022Publication date: November 16, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20230236624Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.Type: ApplicationFiled: January 24, 2022Publication date: July 27, 2023Inventors: Dotan David Levi, Wojciech Wasko, Eitan Zahavi, Natan Manevich, Bar Shapira
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Publication number: 20230231695Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.Type: ApplicationFiled: January 20, 2022Publication date: July 20, 2023Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Publication number: 20230229188Abstract: A system is disclosed that includes two or more network elements, each comprising a Precision Time Protocol (PTP) Hardware Clock (PHC) that is adjustable based, at least in part, on physical layer frequency information.Type: ApplicationFiled: January 18, 2022Publication date: July 20, 2023Inventors: Bar Shapira, Ariel Almog, Dotan David Levi, Natan Manevich, Thomas Kernen
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Patent number: 11706014Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.Type: GrantFiled: January 20, 2022Date of Patent: July 18, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
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Patent number: 11606427Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.Type: GrantFiled: December 14, 2020Date of Patent: March 14, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Avraham Ganor, Arnon Sattinger, Natan Manevich, Reuven Kogan, Artiom Tsur, Ariel Almog, Bar Shapira
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Publication number: 20220191275Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Inventors: Dotan David Levi, Avraham Ganor, Arnon Sattinger, Natan Manevich, Reuven Kogan, Artiom Tsur, Ariel Almog, Bar Shapira