Abstract: A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

Abstract: A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC comprises a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC comprises a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC comprises switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

Abstract: A system (e.g., a transmitter system on chip) comprises a digital-to-analog converter configured to convert an N-bit digital signal to a corresponding analog signal, where N is an integer greater than 1. The digital-to-analog converter may comprise N bias circuits, where each of the bias circuits is configured to generate a bias current, and route the bias current based on a value of a respective one of the N bits of the N-bit digital signal. Each of the N bias circuits may comprises a resistor network and a pair of switching circuits.

Abstract: Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

Abstract: Low noise amplifiers (LNAs) are provided, the LNAs comprising: a common gate matching network; a capacitord; a resistord; a coild, wherein a side1 of coild is coupled to a side1 of capacitord, a side1 of resistord, and a V+ and a side2 of the coild is coupled to a side2 of capacitord, a side2 of resistord, and a network input; a capacitors; a resistors; a coils, wherein a side1 of coils is coupled to an LNA input, a side1 of capacitors, a side1 of resistors, and a network output and a side2 of coils is coupled to a side2 of the capacitors, a side2 of resistors, and ground; and an output coil that is magnetically coupled to coild and coils and having a side1 coupled to a first terminal of an LNA output and a side2 coupled to a second terminal of the LNA output.

Abstract: Low noise amplifiers (LNAs) are provided, the LNAs comprising: a common gate matching network; a capacitord; a resistord; a coild, wherein a side1 of coild is coupled to a side1 of capacitord, a side1 of resistord, and a V+ and a side2 of the coild is coupled to a side2 of capacitord, a side2 of resistord, and a network input; a capacitors; a resistors; a coils, wherein a side1 of coils is coupled to an LNA input, a side1 of capacitors, a side1 of resistors, and a network output and a side2 of coils is coupled to a side2 of the capacitors, a side2 of resistors, and ground; and an output coil that is magnetically coupled to coild and coils and having a side1 coupled to a first terminal of an LNA output and a side2 coupled to a second terminal of the LNA output.

Abstract: Circuits, methods, and media for providing calibrated delta-sigma modulators are provided. In some embodiments, circuits for a delta-sigma modulator are provided, the circuits comprising: an analog-to-digital converter that produces an output having multiple bits; a digital-to-analog converter having an input having multiple bits; a switch coupled between the output the input that can be used to configure connections between the bits of the output and the bits of the input; a hardware processor that: for multiple iterations, sets a configuration of the switch, samples the bits of the output to produce sample values for each bit of the bits of the output, and calculates an average of the sample values for each of the bits of the output values; computes weights for each of the bits of the output values; and calculates weighted output values for every value of the outputs.

Abstract: Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

Abstract: Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an RZ signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.

Abstract: Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an RZ signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.