Patents by Inventor Barak Baum
Barak Baum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230400574Abstract: A technique for determining a presence of a person in a room may include an electronic device transmitting an electromagnetic wireless signal of a first sensor. The technique may include receiving an electromagnetic return signal from the electromagnetic wireless signal. The technique may include detecting a potential target in the room based on the electromagnetic return signal. The technique may include determining that the potential target is in the room using a second sensor. Responsive to determining the potential target is in the room, the technique may include saving a training signature of the electromagnetic return signal for training a machine learning model. This technique can be repeated to obtain a set of training signatures corresponding to potential targets. The technique may include training, using the set of training signatures, the machine learning model to detect when a target is in the room using the first sensor.Type: ApplicationFiled: April 27, 2023Publication date: December 14, 2023Applicant: APPLE INC.Inventors: Barak Baum, Yoav Feinmesser, Naftali Sommer
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Patent number: 10762967Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.Type: GrantFiled: November 28, 2018Date of Patent: September 1, 2020Assignee: APPLE INC.Inventors: Assaf Shappir, Barak Baum, Itay Sagron, Roman Guy, Guy Ben-Yehuda, Stas Mouler
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Publication number: 20200005874Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.Type: ApplicationFiled: November 28, 2018Publication date: January 2, 2020Inventors: Assaf Shappir, Barak Baum, Itay Sagron, Roman Guy, Guy Ben-Yehuda, Stas Mouler
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Patent number: 10332608Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.Type: GrantFiled: May 30, 2018Date of Patent: June 25, 2019Assignee: APPLE INC.Inventors: Yael Shur, Assaf Shappir, Barak Baum, Roman Guy, Michael Tsohar
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Publication number: 20180358103Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.Type: ApplicationFiled: May 30, 2018Publication date: December 13, 2018Inventors: Yael Shur, Assaf Shappir, Barak Baum, Roman Guy, Michael Tsohar
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Publication number: 20180349044Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.Type: ApplicationFiled: September 27, 2017Publication date: December 6, 2018Inventors: Barak Baum, Barak Sagiv, Einav Yogev, Eyal Gurgi, Ariel Landau
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Patent number: 10146460Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.Type: GrantFiled: September 27, 2017Date of Patent: December 4, 2018Assignee: APPLE INC.Inventors: Barak Baum, Barak Sagiv, Einav Yogev, Eyal Gurgi, Ariel Landau
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Patent number: 10008278Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.Type: GrantFiled: June 11, 2017Date of Patent: June 26, 2018Assignee: APPLE INC.Inventors: Yael Shur, Assaf Shappir, Barak Baum, Roman Guy, Michael Tsohar
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Patent number: 9952779Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.Type: GrantFiled: March 1, 2016Date of Patent: April 24, 2018Assignee: APPLE INC.Inventors: Yoni Labenski, Roman Gindin, Etai Zaltsman, Moti Altahan, Yoram Harel, Barak Baum
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Patent number: 9779818Abstract: A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.Type: GrantFiled: July 9, 2015Date of Patent: October 3, 2017Assignee: APPLE INC.Inventors: Barak Baum, Alex Radinski, Eyal Gurgi, Naftali Sommer, Tsafrir Kamelo
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Publication number: 20170255396Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.Type: ApplicationFiled: March 1, 2016Publication date: September 7, 2017Inventors: Yoni Labenski, Roman Gindin, Etai Zaltsman, Moti Altahan, Yoram Harel, Barak Baum
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Patent number: 9697075Abstract: A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.Type: GrantFiled: September 8, 2015Date of Patent: July 4, 2017Assignee: APPLE INC.Inventors: Yonathan Tate, Barak Baum, Moti Teitel
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Patent number: 9672925Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.Type: GrantFiled: March 10, 2016Date of Patent: June 6, 2017Assignee: Apple Inc.Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum
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Publication number: 20170068591Abstract: A method includes storing data encoded with an ECC in a group of memory cells by writing respective storage values to the memory cells. Multiple sets of readout results are read from the memory cells by comparing the storage values to one or more threshold combinations, each including multiple read thresholds. A plurality of partial syndromes of the ECC is computed, each partial syndrome computed over the readout results that were read using a respective threshold combination. A respective syndrome is calculated for each threshold combination, in at least a subset of all possible threshold combinations, based on one or more of the partial syndromes associated with that threshold combination. A preferred threshold combination is selected, from among the threshold combinations, for which a weight of the respective syndrome is minimal, by processing less than all the partial syndromes associated with all the possible threshold combinations.Type: ApplicationFiled: September 8, 2015Publication date: March 9, 2017Inventors: Yonathan Tate, Barak Baum, Moti Teitel
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Publication number: 20170011803Abstract: A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.Type: ApplicationFiled: July 9, 2015Publication date: January 12, 2017Inventors: Barak Baum, Alex Radinski, Eyal Gurgi, Naftali Sommer, Tsafrir Kamelo
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Patent number: 9390809Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.Type: GrantFiled: February 10, 2015Date of Patent: July 12, 2016Assignee: APPLE INC.Inventors: Yael Shur, Avraham Poza Meir, Barak Baum, Eyal Gurgi
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Publication number: 20160189783Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.Type: ApplicationFiled: March 10, 2016Publication date: June 30, 2016Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum
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Patent number: 9349467Abstract: A method includes dividing a group of analog memory cells into multiple subsets. The memory cells in the group are sensed simultaneously by performing a single sense operation, while applying to the subsets of the memory cells respective different sets of read thresholds, so as to produce respective readout results. An optimal set of the read thresholds is estimated by processing the multiple readout results obtained from the respective subsets using the different sets of the read thresholds.Type: GrantFiled: July 28, 2014Date of Patent: May 24, 2016Assignee: Apple Inc.Inventors: Barak Baum, Eyal Gurgi
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Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block
Patent number: 9330783Abstract: An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.Type: GrantFiled: December 17, 2014Date of Patent: May 3, 2016Assignee: APPLE INC.Inventors: Barak Rotbard, Avraham Poza Meir, Eyal Gurgi, Yael Shur, Barak Baum -
Patent number: 9312017Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.Type: GrantFiled: August 12, 2014Date of Patent: April 12, 2016Assignee: Apple Inc.Inventors: Arik Rizel, Avraham Poza Meir, Yael Shur, Eyal Gurgi, Barak Baum