Patents by Inventor Barbara A. Waterhouse
Barbara A. Waterhouse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7754574Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.Type: GrantFiled: October 20, 2006Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Zhong-Xiang He, Wolfgang Sauter, Barbara A. Waterhouse
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Patent number: 7511940Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: GrantFiled: August 15, 2007Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
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Publication number: 20080132026Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the fill metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.Type: ApplicationFiled: October 20, 2006Publication date: June 5, 2008Applicant: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Zhong-Xiang He, Wolfgang Sauter, Barbara A. Waterhouse
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Patent number: 7326987Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.Type: GrantFiled: May 13, 2005Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Wagdi Abadeer, Eric Adler, Zhong-Xiang He, Bradley Orner, Vidhya Ramachandran, Barbara A. Waterhouse, Michael Zierak
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Publication number: 20080019077Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: ApplicationFiled: August 15, 2007Publication date: January 24, 2008Inventors: Douglas Coolbaugh, Ebenezer Eshun, Natalie Feilchenfeld, Michael Gautsch, Zhong-Xiang He, Matthew Moon, Vidhya Rahmachandran, Barbara Waterhouse
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Patent number: 7301752Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: GrantFiled: June 4, 2004Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
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Publication number: 20070120216Abstract: A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.Type: ApplicationFiled: November 30, 2005Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Brigante, Zhong-Xiang He, Barbara Waterhouse, Eric White
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Patent number: 7170181Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.Type: GrantFiled: November 19, 2003Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Zhong-Xiang He, Wolfgang Sauter, Barbara A. Waterhouse
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Patent number: 7056820Abstract: A bond pad upon which a wirebond interconnection is formed, consisting of a first bond pad layer formed on a chip, and a second bond pad layer formed on the first bond pad layer, wherein the first bond pad layer is more resistant to removal than the second bond pad layer during probe testing, and the first bond pad layer increases resistance to interconnection failure during mechanical testing.Type: GrantFiled: November 20, 2003Date of Patent: June 6, 2006Assignee: International Business Machines CorporationInventors: Stephen P. Cole, William J. Murphy, Barbara A. Waterhouse
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Publication number: 20050272219Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: ApplicationFiled: June 4, 2004Publication date: December 8, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Ebenezer Eshun, Natalie Feilchenfeld, Michael Gautsch, Zhong-Xiang He, Matthew Moon, Vidhya Ramachandran, Barbara Waterhouse
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Publication number: 20050189615Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.Type: ApplicationFiled: May 13, 2005Publication date: September 1, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wagdi Abadeer, Eric Adler, Zhong-Xiang He, Bradley Orner, Vidhya Ramachandran, Barbara Waterhouse, Michael Zierak
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Patent number: 6913965Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.Type: GrantFiled: April 15, 2004Date of Patent: July 5, 2005Assignee: International Busniess Machines CorporationInventors: Wagdi W. Abadeer, Eric Adler, Zhong-Xiang He, Bradley Orner, Vidhya Ramachandran, Barbara A. Waterhouse, Michael Zierak
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Publication number: 20050112794Abstract: A bond pad upon which a wirebond interconnection is formed, consisting of a first bond pad layer formed on a chip, and a second bond pad layer formed on the first bond pad layer, wherein the first bond pad layer is more resistant to removal than the second bond pad layer during probe testing, and the first bond pad layer increases resistance to interconnection failure during mechanical testing.Type: ApplicationFiled: November 20, 2003Publication date: May 26, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen Cole, William Murphy, Barbara Waterhouse
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Publication number: 20050104188Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.Type: ApplicationFiled: November 19, 2003Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Zhong-Xiang He, Wolfgang Sauter, Barbara Waterhouse