Abstract: A GNSS receiver having test signal based failure detection, comprises: a signal generator configured to generate a test signal, the test signal having characteristics of a GNSS signal; one of more amplifiers configured to amplify the test signal; a signal chain configured to receive the amplified test signal at an input node of the signal chain and process the received test signal; and a signal processor configured to: monitor the test signal by: obtaining one or more output signals of the device at one or more output node; recovering the test signal from the one or more output signals, and determining whether one or more errors occurred based on parameters of the recovered test signal based on parameters of the recovered test signal; identify a device failure based on the determined one or more errors; and generate notifications relating to the device failure.

Abstract: A GNSS receiver having test signal based failure detection, comprises: a signal generator configured to generate a test signal, the test signal having characteristics of a GNSS signal; one of more amplifiers configured to amplify the test signal; a signal chain configured to receive the amplified test signal at an input node of the signal chain and process the received test signal; and a signal processor configured to: monitor the test signal by: obtaining one or more output signals of the device at one or more output node; recovering the test signal from the one or more output signals, and determining whether one or more errors occurred based on parameters of the recovered test signal based on parameters of the recovered test signal; identify a device failure based on the determined one or more errors; and generate notifications relating to the device failure.

Abstract: A comparator circuit includes a first amplifier stage whose input can be selectively connected to an input voltage and to a reference voltage. A second amplifier stage is connected to the output of the first amplifier and a final stage is connected to the output of the second amplifier stage, at which a rectangular signal is output. The rectangular signal represents times in which the input signal is higher or lower than the reference signal. Both amplifier stages include a first input capacitance having one plate connected to the input of that stage. The other plate of the capacitance is connected to the gate of a transistor and a control switch. Low power dissipation is realized in the circuit by including a follower cascaded with an inverter. This structure allows the same operation as the prior art but offers a better design flexibility since all design parameters are free to be rearranged to achieve the required performance.