Abstract: A data handling system for transferring data between two units, the data being transferred in blocks of a selected number of data words, up to predetermined maximum number. A buffer stores the data being transferred. The buffer includes a plurality of stages arranged serially from an input end to an output end, the number of stages being equal in number to the predetermined maximum number of data words that may be transferred in a block. If the number of data words being transferred is less than the predetermined maximum number, as indicated by a control signal from the unit transmitting the data, the buffer either receives the data in the stage a number of stages from the output end, or transmits the data from the stage a number of stages from the input end, equal to the number of words being transferred in the block.

Abstract: A memory for use in a digital data processing system, the memory including a memory controller and one or more memory arrays. A memory array performs refresh operations transparently to the memory controller, but in synchronization with a system timing signal while it is receiving normal system power. A memory array also includes asynchronous refresh circuitry for controlling refresh while the system power is interrupted and the array receives no system timing signal. When each refresh operation occurs during power interruption, the asynchronous refresh circuitry tests the condition of the system power supply. Since refresh operations are transparent to the memory controller, the memory array indicates when the memory operations are completed. If the memory operation is a read operation, the memory controller then controls the transfer of data from the array to the controller.