Patents by Inventor Barbara Hasler
Barbara Hasler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8581405Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.Type: GrantFiled: June 2, 2011Date of Patent: November 12, 2013Assignees: Infineon Technologies AG, Qimonda AGInventors: Stephan Dertinger, Alfred Martin, Barbara Hasler, Grit Sommer, Florian Binder
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Patent number: 8263491Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.Type: GrantFiled: October 19, 2007Date of Patent: September 11, 2012Assignee: Infineon Technologies AGInventors: Florian Binder, Stephan Dertinger, Barbara Hasler, Alfred Martin, Grit Sommer, Holger Torwesten
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Patent number: 8048801Abstract: A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel.Type: GrantFiled: May 21, 2007Date of Patent: November 1, 2011Assignees: Infineon Technologies, AG, Qimonda AGInventors: Stephan Dertinger, Alfred Martin, Barbara Hasler, Grit Sommer, Florian Binder
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Publication number: 20110233630Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.Type: ApplicationFiled: June 2, 2011Publication date: September 29, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Stephan Dertinger, Alfred Martin, Barbara Hasler, Grit Sommer, Florian Binder
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Patent number: 7977798Abstract: An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element.Type: GrantFiled: July 26, 2007Date of Patent: July 12, 2011Assignees: Infineon Technologies AG, Qimonda AGInventors: Stephan Dertinger, Alfred Martin, Barbara Hasler, Grit Sommer, Florian Binder
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Patent number: 7973417Abstract: An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a first field of the floor of the blind hole, and may also promote wetting of a solder material of the solder connection. Wetting may be impeded on a second field of the floor of the blind hole. The second contact pad may be arranged above a surface of a further substrate, wherein the surface of the further substrate may be oriented perpendicularly to the floor of the blind hole in the substrate.Type: GrantFiled: April 18, 2008Date of Patent: July 5, 2011Assignee: Qimonda AGInventors: Alfred Martin, Barbara Hasler
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Patent number: 7745321Abstract: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.Type: GrantFiled: January 11, 2008Date of Patent: June 29, 2010Assignee: Qimonda AGInventors: Alfred Martin, Barbara Hasler, Martin Franosch, Klaus-Guenter Oppermann
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Publication number: 20090261480Abstract: An article including a substrate having a blind hole formed therein, wherein the blind hole is defined by a floor and a sidewall and a solder connection is provided. The solder connection may couple a first contact pad to a second contact pad. The first contact pad may cover a first field of the floor of the blind hole, and may also promote wetting of a solder material of the solder connection. Wetting may be impeded on a second field of the floor of the blind hole. The second contact pad may be arranged above a surface of a further substrate, wherein the surface of the further substrate may be oriented perpendicularly to the floor of the blind hole in the substrate.Type: ApplicationFiled: April 18, 2008Publication date: October 22, 2009Inventors: Alfred Martin, Barbara Hasler
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Publication number: 20090179333Abstract: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.Type: ApplicationFiled: January 11, 2008Publication date: July 16, 2009Inventors: Alfred Martin, Barbara Hasler, Martin Franosch, Klaus-Guenter Oppermann
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Publication number: 20080268638Abstract: A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel.Type: ApplicationFiled: May 21, 2007Publication date: October 30, 2008Applicants: INFINEON TECHNOLOGIES AG, QIMONDA AGInventors: Stephan Dertinger, Alfred Martin, Barbara Hasler, Grit Sommer, Florian Binder
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Publication number: 20080217784Abstract: A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.Type: ApplicationFiled: October 19, 2007Publication date: September 11, 2008Inventors: Florian Binder, Stephen Dertinger, Barbara Hasler, Alfred Martin, Grit Sommer, Holger Torwesten
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Patent number: 6708405Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.Type: GrantFiled: August 28, 2001Date of Patent: March 23, 2004Assignee: Infineon Technologies AGInventors: Barbara Hasler, Rainer Florian Schnabel, Guenther Schindler, Volker Weinrich
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Publication number: 20020032962Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.Type: ApplicationFiled: August 28, 2001Publication date: March 21, 2002Inventors: Barbara Hasler, Rainer Florian Schnabel, Guenther Schindler, Volker Weinrich
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Patent number: 6309930Abstract: The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G1, G2, G4). Parts of the memory cell such as, for example, gate electrodes (Ga2, Ga4) or conductive structures (L3) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H5) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L3) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D2) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B2) or/and via conductive structures (L1, L2, L6) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K5) contact a plurality of parts of the MOS transistors simultaneously.Type: GrantFiled: November 9, 2000Date of Patent: October 30, 2001Assignee: Siemens AktiengesellschaftInventors: Bernd Goebel, Emmerich Bertagnolli, Josef Willer, Barbara Hasler, Paul-Werner von Basse
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Patent number: 6222753Abstract: An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.Type: GrantFiled: December 20, 1999Date of Patent: April 24, 2001Assignee: Siemens AktiengesellschaftInventors: Bernd Goebel, Emmerich Bertagnolli, Josef Willer, Barbara Hasler, Paul-Werner von Basse
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Patent number: 6118159Abstract: The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.Type: GrantFiled: February 26, 1999Date of Patent: September 12, 2000Assignee: Siemens AktiengesellschaftInventors: Josef Willer, Franz Hofmann, Hans Reisinger, Emmerich Bertagnolli, Bernd Gobel, Barbara Hasler, Karl-Heinz Tietgen
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Patent number: 4479850Abstract: A method for etching a double layer semiconductor structure containing metal silicide layers or a metal silicide-polysilicon layer on a silicon substrate through a photoresist mask by means of reactive ion etching wherein dissociation and ionization of reactant gases take place in a plasma, the improvement which comprises:employing a mixture of chlorine gas and a highly reducing gas such as boron trichloride as the reactant gases.Type: GrantFiled: February 17, 1984Date of Patent: October 30, 1984Assignee: Siemens AktiengesellschaftInventors: Willy Beinvogl, Barbara Hasler
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Patent number: 4380489Abstract: Polysilicon structures down to a 1 .mu.m range on substrates containing integrated semiconductor circuits are produced by plasma etching in a plate reactor with the use of SF.sub.6 and an inert gas as the reactive gas. During this process, a semiconductor crystal wafers (4, 17) covered with a SiO.sub.2 layer (16) and a polysilicon layer (15) is provided with an etch mask (14) and positioned on a grounded electrode of the plate reactor and an etching process, which achieves a high selectivity of polysilicon (15) to SiO.sub.2 (16) and to the etch mask (14), is carried out with a HF power, P, of <0.1 watt/cm.sup.2, a gas pressure, p, ranging from 60 to 120 Pa, and an electrode temperature ranging from 20.degree. to 60.degree. C. With the inventive process, large scale integrated semiconductor circuits are produced in a single stage sequence with high etching selectivity, uniform etching and a high throughput of silicon wafers.Type: GrantFiled: January 21, 1982Date of Patent: April 19, 1983Assignee: Siemens AktiengesellschaftInventors: Willy Beinvogl, Barbara Hasler