Abstract: Multi-phase clock time stamping for improving time stamp resolution is provided. One of many possible embodiments is a method for generating a time stamp having an improved time resolution for an event signal. Briefly described, one such method comprises the steps of: receiving an event signal for which a time stamp is to be generated; generating a first pulse signal having a pulse width defined by the event signal and a first clock signal; generating a second pulse signal having a pulse width defined by the event signal and a second clock signal; and determining which of the first pulse signal and the second pulse signal is to be used for generating the time stamp for the event signal.

Abstract: Variable delay circuits and methods for delaying a waveform by an adjustable time delay are disclosed herein. One such variable delay circuit comprises a delay range limitation circuit having a first differential input, a first differential output, and a second differential output. The first differential input is configured to receive an input waveform. The first differential output is configured to output the waveform with a maximum delay, and the second differential output is configured to output the waveform with a minimum delay. The variable delay circuit further comprises a delay mixing circuit having second and third differential inputs, first and second control inputs, and a third differential output. The second differential input is connected to the first differential output. The third differential input is connected to the second differential output. The first and second control inputs are configured to receive control voltages V1 and V2, which are related to a selected time delay.

Abstract: A dual mode amplifier having single ended and differential ended modes of operation using only one set of output pads or terminals. The dual mode amplifier has two differential amplifiers, connected by coupling circuitry, each differential amplifier receiving a pair of differential input signals and having one output terminal. By activating and deactivating the coupling circuitry, the differential amplifiers can operate in two modes using the one set of output terminals. In the singled ended mode, the differential amplifiers operate independently, each converting the differential input signals to a singled ended output signal at their respective output terminals. In the differential mode, the differential amplifiers operate together to provide a pair of differential output signals at the output terminals based upon the pair of input signals.

Abstract: Variable delay circuits and methods for delaying a waveform by an adjustable time delay are disclosed herein. One such variable delay circuit comprises a delay range limitation circuit having a first differential input, a first differential output, and a second differential output. The first differential input is configured to receive an input waveform. The first differential output is configured to output the waveform with a maximum delay, and the second differential output is configured to output the waveform with a minimum delay. The variable delay circuit further comprises a delay mixing circuit having second and third differential inputs, first and second control inputs, and a third differential output. The second differential input is connected to the first differential output. The third differential input is connected to the second differential output. The first and second control inputs are configured to receive control voltages V1 and V2, which are related to a selected time delay.

Abstract: Multi-phase clock time stamping for improving time stamp resolution is provided. One of many possible embodiments is a method for generating a time stamp having an improved time resolution for an event signal. Briefly described, one such method comprises the steps of: receiving an event signal for which a time stamp is to be generated; generating a first pulse signal having a pulse width defined by the event signal and a first clock signal; generating a second pulse signal having a pulse width defined by the event signal and a second clock signal; and determining which of the first pulse signal and the second pulse signal is to be used for generating the time stamp for the event signal.

Abstract: Systems for altering the timing of edges of an input signal for altering the position in time of timing edges of an input signal are disclosed. Such a system includes a differential amplifier having positive and negative inputs and outputs. The differential amplifier includes a symmetrical differential field effect transistor (FET) pair, each FET transistor of the pair having drain, source, and gate electrodes, wherein the source electrodes of the FET transistors are connected together. The differential amplifier also includes active loads coupled to the drain electrodes of the FET transistors and configured to be controllably biased to offset effects to the delay element caused by a plurality of operating variations. The delay element also includes variable capacitance banks connected to the outputs of the differential amplifier and configured to supply a selected capacitance to the outputs so as to delay and thereby alter the timing edges of the input signal. Methods and other systems also are provided.

Abstract: A dual mode amplifier having single ended and differential ended modes of operation using only one set of output pads or terminals. The dual mode amplifier has two differential amplifiers, connected by coupling circuitry, each differential amplifier receiving a pair of differential input signals and having one output terminal. By activating and deactivating the coupling circuitry, the differential amplifiers can operate in two modes using the one set of output terminals. In the singled ended mode, the differential amplifiers operate independently, each converting the differential input signals to a singled ended output signal at their respective output terminals. In the differential mode, the differential amplifiers operate together to provide a pair of differential output signals at the output terminals based upon the pair of input signals.

Abstract: A high-precision high-linearity digital-to-analog converter (DAC) and a method for converting a digital input signal having N bits to a substantially equivalent analog current output signal is presented. The DAC segments the digital input signal bits into groups separate processing. The invention includes a first current-steering digital-to-analog converter configured to receive a first group of i input signal bits and a first reference current to produce a first current signal. A second current-steering digital-to-analog converter is configured to receive a second group of j input signal bits and the first reference current to produce an intermediate current signal. The intermediate current signal is scaled down by a factor of 2j to produce a second current signal. A summing circuit sums at least the first and second current signals to produce an analog current signal representative of the digital input signal value.

Abstract: A dual mode amplifier having single ended and differential ended modes of operation using only one set of output pads or terminals. The dual mode amplifier has two differential amplifiers, connected by coupling circuitry, each differential amplifier receiving a pair of differential input signals and having one output terminal. By activating and deactivating the coupling circuitry, the differential amplifiers can operate in two modes using the one set of output terminals. In the singled ended mode, the differential amplifiers operate independently, each converting the differential input signals to a singled ended output signal at their respective output terminals. In the differential mode, the differential amplifiers operate together to provide a pair of differential output signals at the output terminals based upon the pair of input signals.

Abstract: Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals.

Abstract: A method and apparatus are provided for accomplishing virtual deskewing of device-under-test data received by a test system by skewing clock signals instead. In a preferred embodiment, the invention includes a receiver circuit which is capable of operating in a window compare mode to capture a transition of a data signal from either a low data state to a high data state or a high data state to a low data state. The receiver circuit receives a high-level comparator signal and a low-level comparator signal, which when properly deskewed, together indicate what state the data signal is in.