Abstract: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines. The managing logic includes a control block for generating a first enable signal of the precharge step and a second enable signal of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.

Abstract: The semi-conductor memory includes a memory device to store digital data being provided with a first number of intermediate output ports including a first intermediate output port. Furthermore, the memory includes a register block that can be selectively connected to the first intermediate output port to store data in the memory device and a second number of output ports including first and second output ports. The memory includes an interface device to receive strobe signals from the memory device, each being indicative of the presence of data on the at least one intermediate output port. This interface device, based on the strobe signals, controls the register block to provide the data stored in the register on the first and second output ports, by emulating a multi-port memory where the second number is greater than the first number.

Abstract: A memory device an array of memory cells, the array including word lines and bit lines. The memory device also includes managing logic for managing array reading operations that are carried out by executing a step of precharging the bit lines and a step of turning on the word lines. The managing logic includes a control block for generating a first enable signal of the precharge step and a second enable signal of the turning on step such that, within the same reading operation, the precharge and turning on steps are partially concurrent.

Abstract: The semi-conductor memory includes a memory device to store digital data being provided with a first number of intermediate output ports including a first intermediate output port. Furthermore, the memory includes a register block that can be selectively connected to the first intermediate output port to store data in the memory device and a second number of output ports including first and second output ports. The memory includes an interface device to receive strobe signals from the memory device, each being indicative of the presence of data on the at least one intermediate output port. This interface device, based on the strobe signals, controls the register block to provide the data stored in the register on the first and second output ports, by emulating a multi-port memory where the second number is greater than the first number.