Abstract: An integrated module assembly can include: an optical integrated circuit having first and second optical devices; a PCB having first and second holes therein, where the optical integrated circuit is coupled upside down to a first side of the PCB; and first and second lenses coupled to a second side of the PCB, where the first and second sides of the PCB are opposite thereto; and where the first lens is in alignment with the first hole and the first optical device, and the second lens is in alignment with the second hole and the second optical device.

Abstract: A memory device, can include: a control circuit configured to operate the memory device in one of an active mode, a standby mode, and a sleep mode, where the memory device is configured to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device, where the voltage regulator is off during the sleep mode and the standby mode, and the voltage regulator is on during the active mode; and a storage element configured to maintain the supply voltage to allow the voltage regulator to be turned off during the standby mode, and at least until the voltage regulator turns on in the active mode and supports the supply voltage.

Abstract: An integrated module assembly can include: an optical integrated circuit having first and second optical devices; a PCB having first and second holes therein, where the optical integrated circuit is coupled upside down to a first side of the PCB; and first and second lenses coupled to a second side of the PCB, where the first and second sides of the PCB are opposite thereto; and where the first lens is in alignment with the first hole and the first optical device, and the second lens is in alignment with the second hole and the second optical device.

Abstract: A memory device can include: a non-volatile storage register configured to store an active reset polling enable bit that corresponds to a reset operation; a controller configured to control execution of the reset operation on the memory device; an operation completion indicator configured to provide a reset recovery indication external to the memory device when the reset operation has completed and the active reset polling enable bit is set; and a command decoder configured to receive a command to be executed on the memory device in response to the reset recovery indication.

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

Abstract: A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.

Abstract: A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.

Abstract: A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.

Abstract: A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.