Abstract: In one embodiment, a circuit, having a single supply, is provided to transmit a wireless signal with low common mode electromagnetic interference (EMI) emission. The circuit can achieve common mode attenuations of 40 dB or greater as a result of the symmetric built circuit. Also included is a system that includes a transmission circuit and a receiver circuit, and a method of using such a system.

Abstract: In one embodiment, a circuit, having a single supply, is provided to transmit a wireless signal with low common mode electromagnetic interference (EMI) emission. The circuit can achieve common mode attenuations of 40 dB or greater as a result of the symmetric built circuit. Also included is a system that includes a transmission circuit and a receiver circuit, and a method of using such a system.

Abstract: A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a linear range after a change in the frequency of said frequency modulated signals (uDIV) to a desired frequency. The lock time of the phase-locked loop circuit is improved without the requirement of complex circuitry.

Abstract: The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a “1”, and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.

Abstract: A variable frequency synthesizer comprising a sigma-delta modulator is provided. Such synthesizers provide an exact average frequency whereas the instantaneous frequencies varies. The sigma-delta modulator comprises a plurality of accumulator stages being connected in cascade. At least one input value of an accumulator (51, 52, 53, 54) being part of the sigma-delta modulator has a second component which is equal to an overflow signal (of1, of2, of3, of4) multiplied by a factor. This feedback reduces the-maximum fluctuation of the instantaneous frequencies. Phase jitter generated by non-linearities of the phase detector, the charge pump and the VCO is therefore reduced.