Abstract: A multiprocessor system comprising a plurality of processors and a memory unit which are connected through a common bus whereby each processor communicates with the memory through the bus. Communication among processors is effected by storing in a plurality of memory zones the messages intended for the several processors. The memory zones are each dedicated to one processors, but are accessible to all the processors. The communication among processors is performed by sending a notify signal on the common bus which is identified only by the processor for which it is intended. The notify signal is acknowledged by the notified processor without interrupting its ongoing operation. The notified processor subsequently accesses the memory unit and reads the message in the appropriate memory zone.