Patents by Inventor Baris Taskin
Baris Taskin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11329362Abstract: On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. A Through-Silicon Via (TSV)-based antenna design called TSV_A establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30 mm on-chip distance. Simulation results show an improvement in network latency up to ˜13% (average improvement of ˜7%), energy-delay improvements of ˜34% on average, and an improvement in throughput up to ˜34% (average improvement).Type: GrantFiled: December 18, 2019Date of Patent: May 10, 2022Assignee: Drexel UniversityInventors: Vasil Pano, Ibrahim Tekin, Baris Taskin, Kapil R. Dandekar, Yuqiao Liu
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Patent number: 11243559Abstract: Modern integrated circuits have an increasing need for various levels of both supply voltage (V) and operating frequency (f) available at fine spatial and temporal granularity. This work introduces a solution that provides a number and quality of locally distributed V/f domains through FOPAC. Opportunistically sharing design resources and features between multi-phase voltage regulators (MPVRs) and resonant rotary clocks (ReRoCs) enabling i) the scalability to hundreds of domains, ii) fast switching times for both voltage and frequency, leading to temporal flexibility, and iii) locally distributed designs, leading to spatial flexibility.Type: GrantFiled: May 29, 2020Date of Patent: February 8, 2022Assignee: Drexel UniversityInventors: Baris Taskin, Ragh Kuttappa, Selcuk Kose
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Publication number: 20210034094Abstract: Modern integrated circuits have an increasing need for various levels of both supply voltage (V) and operating frequency (f) available at fine spatial and temporal granularity. This work introduces a solution that provides a number and quality of locally distributed V/f domains through FOPAC. Opportunistically sharing design resources and features between multi-phase voltage regulators (MPVRs) and resonant rotary clocks (ReRoCs) enabling i) the scalability to hundreds of domains, ii) fast switching times for both voltage and frequency, leading to temporal flexibility, and iii) locally distributed designs, leading to spatial flexibility.Type: ApplicationFiled: May 29, 2020Publication date: February 4, 2021Applicants: Drexel University, University of South FloridaInventors: Baris Taskin, Ragh Kuttappa, Selcuk Kose
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Publication number: 20200212538Abstract: On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. A Through-Silicon Via (TSV)-based antenna design called TSV_A establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30 mm on-chip distance. Simulation results show an improvement in network latency up to ˜13% (average improvement of ˜7%), energy-delay improvements of ˜34% on average, and an improvement in throughput up to ˜34% (average improvement).Type: ApplicationFiled: December 18, 2019Publication date: July 2, 2020Applicant: Drexel UniversityInventors: Vasil Pano, Ibrahim Tekin, Baris Taskin, Kapil R. Dandekar, Yuqiao Liu
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Patent number: 10338633Abstract: A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.Type: GrantFiled: June 13, 2017Date of Patent: July 2, 2019Assignees: Drexel University, Stony Brook UniversityInventors: Weicheng Liu, Emre Salman, Ahmet Can Sitik, Baris Taskin
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Patent number: 9866174Abstract: A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.Type: GrantFiled: November 1, 2016Date of Patent: January 9, 2018Assignee: Drexel UniversityInventors: Baris Taskin, Ying Teng
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Publication number: 20170357286Abstract: A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.Type: ApplicationFiled: June 13, 2017Publication date: December 14, 2017Applicants: Drexel University, Stony Brook UniversityInventors: Weicheng Liu, Emre Salman, Ahmet Can Sitik, Baris Taskin
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Publication number: 20170351797Abstract: One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n?1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.Type: ApplicationFiled: August 21, 2017Publication date: December 7, 2017Applicant: DREXEL UNIVERSITYInventors: Baris TASKIN, Ahmet Can SITIK
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Patent number: 9773079Abstract: One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n?1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.Type: GrantFiled: April 28, 2015Date of Patent: September 26, 2017Assignee: Drexel UniversityInventors: Baris Taskin, Ahmet Can Sitik
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Publication number: 20170047892Abstract: A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.Type: ApplicationFiled: November 1, 2016Publication date: February 16, 2017Applicant: Drexel UniversityInventors: Baris Taskin, Ying Teng
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Patent number: 9484896Abstract: A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.Type: GrantFiled: October 6, 2015Date of Patent: November 1, 2016Assignee: Drexel UniversityInventors: Baris Taskin, Ying Teng
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Publication number: 20160099708Abstract: A dynamic rotary traveling wave oscillator circuit includes plurality of multi-output spot-advancing blocks (MOSABs) forming a main-loop and a plurality of multi-input spot-advancing blocks (MISABs) forming a sub-loop. Depending on a desired division ratio, a connection connects blocks on the MOSABs and MISABs to create the desired division ratio.Type: ApplicationFiled: October 6, 2015Publication date: April 7, 2016Inventors: Baris Taskin, Ying Teng
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Publication number: 20150310153Abstract: One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n?1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.Type: ApplicationFiled: April 28, 2015Publication date: October 29, 2015Applicant: Drexel UniversityInventors: Baris Taskin, Ahmet Can Sitik
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Patent number: 9059264Abstract: Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element.Type: GrantFiled: September 26, 2012Date of Patent: June 16, 2015Assignee: Drexel UniversityInventors: Jonathan E Spanier, Guannan Chen, Eric M Gallo, Baris Taskin
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Patent number: 8704577Abstract: A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.Type: GrantFiled: May 25, 2012Date of Patent: April 22, 2014Assignee: Drexel UniversityInventors: Baris Taskin, Jianchao Lu
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Publication number: 20130075702Abstract: Provided are multimaterial devices, such as coaxial nanowires, that effect hot photoexcited electron transfer across the interface of the materials. Modulation of the transfer rates, manifested as a large tunability of the voltage onset of negative differential resistance and of voltage-current phase, may be effected by modulating electrostatic gating, incident photon energy, and the incident photon intensity. Dynamic manipulation of this transfer rate permits the introduction and control of an adjustable phase delay within a device element.Type: ApplicationFiled: September 26, 2012Publication date: March 28, 2013Inventors: Jonathan E. Spanier, Guannan Chen, Eric M. Gallo, Baris Taskin
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Publication number: 20120299627Abstract: A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.Type: ApplicationFiled: May 25, 2012Publication date: November 29, 2012Applicant: DREXEL UNIVERSITYInventors: Baris Taskin, Jianchao Lu