Abstract: In some embodiments, an analog-to-digital converter (ADC) architecture can be implemented to process a signal from a charge output sensor. The ADC architecture can include a summing node for receiving a sensor signal from the charge output sensor, and an output node implemented to provide a digital signal representative of the sensor signal. The ADC architecture can further include a charge amplifier implemented to receive an analog signal from the summing node as an input analog signal and generate an output analog signal with a gain, and an ADC circuit implemented to generate the digital signal based on the output analog signal from the charge amplifier. The ADC architecture can further include a feedback circuit implemented between the output node and the summing node.

Abstract: A system includes an amplification circuit and offset calibration circuit. The amplification circuit includes a modulation circuit operable to modulate a received signal, an amplifier operable to amplify the modulated signal, and a modulation circuit operable to demodulate the amplified signal. The offset calibration circuit includes a logic circuit operable to set a control signal and adjust the control signal based on an output of the amplification circuit, where the output is based on the demodulated signal, and a compensation signal generator operable to generate a compensation signal based on the control signal to compensate for an offset associated with the amplification circuit, and apply the compensation signal on the amplification circuit to adjust the output of the amplification circuit. The offset calibration circuit in conjunction with the application circuit reduces flicker, offset, and offset drift, and also suppresses the upmodulate ripple due to chopping.

Abstract: A system includes an amplification circuit and offset calibration circuit. The amplification circuit includes a modulation circuit operable to modulate a received signal, an amplifier operable to amplify the modulated signal, and a modulation circuit operable to demodulate the amplified signal. The offset calibration circuit includes a logic circuit operable to set a control signal and adjust the control signal based on an output of the amplification circuit, where the output is based on the demodulated signal, and a compensation signal generator operable to generate a compensation signal based on the control signal to compensate for an offset associated with the amplification circuit, and apply the compensation signal on the amplification circuit to adjust the output of the amplification circuit. The offset calibration circuit in conjunction with the application circuit reduces flicker, offset, and offset drift, and also suppresses the upmodulate ripple due to chopping.

Abstract: An on-chip DC voltage generator and hardware efficient method provide for generating linear DC voltages with a programmable negative temperature coefficient. A temperature-dependent DC voltage is digitally derived from an on-chip temperature readout, a programmable digital word to control the temperature coefficient and a programmable digital word to adjust the digital level. The digital result is applied to a resistor string digital to analog converter (DAC) to generate an analog DC voltage with a negative temperature slope. Additionally, another programmable digital word for trimming allows convergence at a given temperature of voltages having a common level but different temperature coefficients. These voltages can be applied to the word line in the flash memory and track the threshold voltage of the memory cell, which has a negative temperature coefficient, such that the difference between the gate voltage and the threshold voltage is constant over temperature.

Abstract: An on-chip DC voltage generator and hardware efficient method provide for generating linear DC voltages with a programmable negative temperature coefficient. A temperature-dependent DC voltage is digitally derived from an on-chip temperature readout, a programmable digital word to control the temperature coefficient and a programmable digital word to adjust the digital level. The digital result is applied to a resistor string digital to analog converter (DAC) to generate an analog DC voltage with a negative temperature slope. Additionally, another programmable digital word for trimming allows convergence at a given temperature of voltages having a common level but different temperature coefficients. These voltages can be applied to the word line in the flash memory and track the threshold voltage of the memory cell, which has a negative temperature coefficient, such that the difference between the gate voltage and the threshold voltage is constant over temperature.