Patents by Inventor Barrett J. Brickner

Barrett J. Brickner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9384556
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a foreground processing module utilizing the image processing circuitry and the memory. The foreground processing module is configured to obtain one or more images, to estimate a foreground region of interest from the one or more images, to determine a plurality of segments of the foreground region of interest, to calculate amplitude statistics for respective ones of the plurality of segments, to classify respective segments as being respective portions of static foreground objects or as being respective portions of dynamic foreground objects based at least in part on the calculated amplitude statistics and one or more defined patterns for known static and dynamic objects, and to remove one or more segments classified as static foreground objects from the foreground region of interest.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ivan Leonidovich Mazurenko, Denis Vladimirovich Parkhomenko, Pavel Aleksandrovich Aliseitchik, Barrett J. Brickner, Dmitry Nicolaevich Babin
  • Publication number: 20150310622
    Abstract: In one embodiment, an image processor is configured to obtain phase images, and to group the phase images into pseudoframes with each of at least a subset of the pseudoframes comprising multiple ones of the phase images and having as a first phase image thereof one of the phase images that is not a first phase image of an associated depth frame. A velocity field is estimated by comparing corresponding phase images in respective ones of the pseudoframes. Phase images of one or more pseudoframes are modified based at least in part on the estimated velocity field, and one or more depth images are generated based at least in part on the modified phase images. By way of example, different groupings of the phase images into pseudoframes may be used for each obtained phase image, allowing depth images to be generated at much higher rates than would otherwise be possible.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 29, 2015
    Inventors: Alexander Borisovich Kholodenko, Barrett J. Brickner, Denis Vladimirovich Zaytsev, Denis Vasilyevich Parfenov, Alexander Alexandrovich Petyushko
  • Publication number: 20150269740
    Abstract: An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a foreground processing module utilizing the image processing circuitry and the memory. The foreground processing module is configured to obtain one or more images, to estimate a foreground region of interest from the one or more images, to determine a plurality of segments of the foreground region of interest, to calculate amplitude statistics for respective ones of the plurality of segments, to classify respective segments as being respective portions of static foreground objects or as being respective portions of dynamic foreground objects based at least in part on the calculated amplitude statistics and one or more defined patterns for known static and dynamic objects, and to remove one or more segments classified as static foreground objects from the foreground region of interest.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 24, 2015
    Inventors: Ivan Leonidovich Mazurenko, Denis Vladimirovich Parkhomenko, Pavel Aleksandrovich Aliseitchik, Barrett J. Brickner, Dmitry Nicolaevich Babin
  • Publication number: 20140380223
    Abstract: A processing device is configured to provide a user interface comprising a radial layout soft keypad. The radial layout soft keypad comprises a central region and one or more concentric groupings of keys arranged around the central region. For example, the one or more concentric groupings of keys may be arranged as multiple concentric circular rows of keys substantially surrounding the central region, with all of the keys of the concentric circular rows being simultaneously visible in the radial layout soft keypad. The radial layout soft keypad is illustratively presented on a display associated with the processing device and a user interacts with the radial layout soft keypad by making hand gestures in free space in a field of view of an image sensor. A gesture of a first type controls selection of a key and gestures of second and third types control acceptance and rejection of the selected key.
    Type: Application
    Filed: November 26, 2013
    Publication date: December 25, 2014
    Applicant: LSI Corporation
    Inventors: Dustin Counsell, Hieu D. Pham, James F. MacDonald, Barrett J. Brickner
  • Publication number: 20140267004
    Abstract: A method for adjusting an active area of a sensor's field of view by recognizing a touch-less adjust gesture. The method includes receiving data from a sensor having a field of view. The method also includes performing at least one gesture recognition operation upon receiving data from the sensor. The method additionally includes recognizing an adjust gesture by a user. The adjust gesture is a touch-less gesture performed in the field of view by the user to adjust the active area of the field of view. The method further includes adjusting the active area in response to recognizing the adjust gesture by the user.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LSI CORPORATION
    Inventor: Barrett J. Brickner
  • Patent number: 7610019
    Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 27, 2009
    Assignee: DSP Group Inc.
    Inventors: Jaekyun Moon, Younggyun Kim, Barrett J. Brickner, Paul C. Edwards, Michael E. Butenhoff
  • Patent number: 7555512
    Abstract: A wireless communication technique enables fast Fourier transforms (FFTs) and inverse fast Fourier transforms (IFFTs) to be performed with reduced latency and reduced memory requirements. In particular, an FFT/IFFT unit receives input data representative of a communication symbol. The FFT/IFFT unit applies an FFT operation to the input data to generate intermediate data. The FFT/IFFT unit stores the intermediate data in a random access memory (RAM). The intermediate data stored in the RAM may override data used as input to the FFT operation. The FFT/IFFT unit selectively addresses the RAM to retrieve the intermediate data in a desired output order. For example, the FFT/IFFT unit may output the intermediate data in the same sequential order as the FFT/IFFT unit received the input data.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: June 30, 2009
    Assignee: DSP Group Inc.
    Inventors: Ying Chen, Barrett J Brickner
  • Patent number: 7173990
    Abstract: A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: February 6, 2007
    Assignee: DSP Group Inc.
    Inventors: Younggyun Kim, Farshid R Rad, Barrett J Brickner, Jaekyun Moon
  • Patent number: 7146134
    Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: December 5, 2006
    Assignee: DSP Group Inc.
    Inventors: Jaekyun Moon, Younggyun Kim, Barrett J Brickner, Paul C Edwards, Michael E Butenhoff
  • Publication number: 20030153358
    Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.
    Type: Application
    Filed: April 4, 2002
    Publication date: August 14, 2003
    Inventors: Jaekyun Moon, Younggyun Kim, Barrett J. Brickner, Paul C. Edwards, Michael E. Butenhoff
  • Publication number: 20030123582
    Abstract: A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.
    Type: Application
    Filed: May 6, 2002
    Publication date: July 3, 2003
    Inventors: Younggyun Kim, Farshid R. Rad, Barrett J. Brickner, Jaekyun Moon
  • Publication number: 20030053568
    Abstract: A decoder rescales state metric values to avoid overflow by resetting a bit in state metric registers that store the state metric values for each state. For example, the decoder may monitor a most significant bit (MSB) of the state metric registers to determine when the state metric values for all of the states exceed a threshold value. Upon exceeding the threshold value, the decoder may rescale the state metric values to avoid overflow. For instance, when the state metric values exceed the threshold value, the MSBs of the state metric registers may be reset. Resetting the MSBs is equivalent to subtracting half of the maximum value of the state metric register. The resealing technique can prevent state metric value overflow while offering reduced complexity and reduced latency.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 20, 2003
    Inventors: Farshid Rafiee Rad, Barrett J. Brickner
  • Publication number: 20030050945
    Abstract: A wireless communication technique enables fast Fourier transforms (FFTs) and inverse fast Fourier transforms (IFFTs) to be performed with reduced latency and reduced memory requirements. In particular, an FFT/IFFT unit receives input data representative of a communication symbol. The FFT/IFFT unit applies an FFT operation to the input data to generate intermediate data. The FFT/IFFT unit stores the intermediate data in a random access memory (RAM). The intermediate data stored in the RAM may override data used as input to the FFT operation. The FFT/IFFT unit selectively addresses the RAM to retrieve the intermediate data in a desired output order. For example, the FFT/IFFT unit may output the intermediate data in the same sequential order as the FFT/IFFT unit received the input data.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 13, 2003
    Inventors: Ying Chen, Barrett J. Brickner
  • Patent number: 6388587
    Abstract: A data storage channel encoder includes a data word input, a code word output and an encoder. The encoder is coupled between the data word input and the code word output and is adapted to encode successive data words received on the data word input into successive code words on the code word output according to a selected code having combined maximum transition run and parity constraints. The maximum transition run constraint constrains the successive code words such that, when the successive code words are concatenated to form an encoded bit stream, the encoded bit stream has a maximum of one consecutive transition beginning at either odd or even indexed bit positions in the encoded bit stream and a maximum of two consecutive transitions beginning at the other of the odd or even indexed bit positions.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: May 14, 2002
    Assignee: Seagate Technology LLC
    Inventors: Barrett J. Brickner, Pradeep R. Padukone
  • Patent number: 5956195
    Abstract: An information handling system, such as a magnetic disk drive, includes a data channel which has a method and apparatus for detecting binary symbols from a received signal subject to intersymbol interference and additive white Gaussian noise using a three dimensional observation space with orthogonal coordinate axes. Each of three consecutive synchronous observation samples of the received signal corresponding unambiguously to an axis in the observation space. A decision feedback equalizer removes intersymbol interference terms associated with prior detector outputs. A plurality of linear classifiers are used to partition the observation space. The second and/or third sample of the equivalent channel response is constrained relative to the first for the purpose of simplifying the linear classifiers. Boolean logic functions to decide into which decision region of the observation space a sample maps into.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: September 21, 1999
    Assignee: Regents of the University of Minnesota
    Inventors: Barrett J. Brickner, Jaekyun Moon
  • Patent number: 5859601
    Abstract: Apparatus and method for coding to improve the minimum distance properties of sequence detectors operating at high densities in storage systems is presented. The coding scheme of the present invention is referred to as maximum transition run (MTR) code and eliminates data patterns producing long runs of consecutive transitions while imposing the usual k constraint necessary for timing recovery. The code has a distance gaining property similar to an existing (1,k) runlength-limited (RLL) code, but can be implemented with considerably higher code rates. When the MTR code is used with fixed delay tree search (FDTS) or high order partial response maximum likelihood (PRML) detectors, the bit error rate performance improves significantly over existing combinations of codes and detectors.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: January 12, 1999
    Assignee: Regents of the University of Minnesota
    Inventors: Jaekyun Moon, Barrett J. Brickner