Patents by Inventor Barry A. Alcorn

Barry A. Alcorn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6291978
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, the driver of a first test channel applies a test signal to a selected node of the plurality of nodes. A predetermined amount of time after application of the test signal, the receiver of the first test channel reads a node voltage of the selected node. The node voltage is then compared to a predetermined threshold voltage of the receiver of the first test channel, and the result of the comparison is an indication as to whether the selected node is coupled to ground.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: September 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6191570
    Abstract: A method for testing node isolation on a circuit board. The method utilizes an automated test system having a plurality of test channels, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver, to a number of switches, and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. The number of switches are configured to selectively couple the first output and second input to ground. During a node isolation test, each node of a test node group is coupled to one of the test channels. But for a selected node of the test node group, each node of the test node group is coupled to ground via the number of switches of the test channels coupled to the nodes.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: February 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 6051979
    Abstract: A method for testing node interconnection on a circuit board. The method utilizes an automated test system having at least one test channel, wherein each test channel has a digital driver with a first input and a first output, and a digital receiver with a second output and a second input. The second input of the receiver is coupled to the first output of the driver and to a test probe. The test probe is configured to couple the driver and receiver to one of a plurality of nodes on a circuit board. During a node interconnection test, a first selected node is coupled to a first test channel, and it is determined whether the first selected node is connected to ground. If the first selected node is not connected to ground, a second selected node is connected to ground; a test signal is applied to the first selected node via the digital driver of the first test channel; and it is determined whether the first selected node is connected to the second selected node.
    Type: Grant
    Filed: July 25, 1999
    Date of Patent: April 18, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5977775
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node, at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: November 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5504432
    Abstract: An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: April 2, 1996
    Assignee: Hewlett-Packard Company
    Inventors: Kevin G. Chandler, Barry A. Alcorn, Bryan D. Boswell, John M. Heumann, Ed O. Schlotzhauer
  • Patent number: 5164663
    Abstract: A system for providing receiver termination in automatic test equipment wherein the automatic test equipment is capable of testing a plurality of devices under test. The automatic test equipment has a plurality of receivers each of which is connected to the receiver termination system of the present invention. The system selectively connects each receiver termination to one of a plurality of devices under test. Each of the receiver terminations is connected between one of the automatic test equipment receivers and the analog multiplexor and provides a high reference voltage clamping value for clamping signals appearing on the input to the receiver at the high reference value tailored for the specific device under test. It also provides a low reference voltage for clamping signals appearing on the input of the receiver at a low reference voltage value tailored to the device under test.
    Type: Grant
    Filed: December 5, 1990
    Date of Patent: November 17, 1992
    Assignee: Hewlett-Packard Company
    Inventor: Barry A. Alcorn