Abstract: Hybrid parallel internally pipelined Vector Image Processors (24, 41, 54) which may also be externally pipelined. The exemplary Processors (24, 41, 54) include n processing elements (PE.sub.a -PE.sub.n)--wherein "n" is any whole integer but, when greater than "1", the elements are arranged in parallel in a one-dimensional column--for processing a two-dimensional XY PIXEL image array (25, 25', 38, 52) wherein each element (PE.sub.a -PE.sub.n) includes: (i) multiple cascaded latches (N1, N2, N3) in a one-dimensional row; (ii) a neighborhood functional unit (NFU.sub.n) for performing NEIGHBORHOOD TRANSFORMS; (iii) an arithmetic logic unit (ALU) for performing ARTIHMETIC/LOGIC TRANSFORMS; (iv) means (48.sub.n, 49.sub.n, 50.sub.n) for transferring data in the latches (N1, N2, N3) to the neighborhood functional unit (NFU.sub.n) and to the neighboring north/south processors; (v) means (48.sub.n, 49.sub.n) for transferring data in the latches (N1, N2) to the arithmetic logic unit (ALU); and (vi), means (48.sub.n-1 .

Abstract: A network of computing nodes is connected by communication channels into fully-interconnected units and groups of units. Each unit has one and only one direct connection to each other unit in a group, and any one computing node in any unit has a direct connection to at most one other unit. The nodes are suitably computing networks themselves so there can be any number of levels of recursion. In a method of routing and transferring information, each node is given an address having address portions respectively identifying its location at each level of recursion. The information is sent from that port of the sending node which has a port identification identical to the highest order address portion in the destination address which is different from the corresponding address portion of the sending computing node.