Abstract: An invention is provided for data bit align. The invention includes a multiplexer that receives a data sample word as data input and also receives a clock sample word as select input. The multiplexer selects a data bit from the data sample word based on the clock sample word. Generally, the multiplexer can select the data bit from the data sample word corresponding to a position of the clock edge in the clock sample word. The invention also includes an output register, which is coupled to the multiplexer. The output register stores the selected data bit from the multiplexer and provides the selected data bit to remaining system components.

Abstract: The present invention provides a dual stage digital filter and a method for filtering digital data signals. The dual stage digital filter includes a pre-filter, a main filter, and an output register. The pre-filter receives a set of first data bits as inputs and is arranged to filter single noise bits from the set of input data bits to output a set of second data bits. The main filter is coupled to receive the set of second data bits as inputs and is arranged to filter burst noise bits from the set of second data bits to output a set of third data bits. The output register is coupled to receive and store the set of third data bits for output.

Abstract: An apparatus for correcting duty cycle error is provided which includes circuitry capable of determining existence of a duty cycle error from input data received over data transmissions lines where the circuitry generates duty cycle correction data based on the duty cycle error. The apparatus also includes a digital analog converter (DAC) being coupled to the circuitry where the DAC is capable of receiving a magnitude portion of the duty cycle correction data from the circuitry. The apparatus further includes an adjustable bias driver being coupled to the circuitry, the DAC and the data transmission lines. The adjustable bias driver receives the magnitude portion of the duty cycle correction data from the DAC and receives a polarity portion of the duty cycle correction data from the circuitry where the adjustable bias driver adjusts the polarity of signals applied to the data transmission lines for correcting the duty cycle error.

Abstract: An invention is provided for a deskewer that corrects skew on a data channel. The deskewer includes a delay calculator that calculates deskew data indicating the amount of delay needed to correct skew on a data channel. Coupled to the delay calculator is a deskew circuit that receives the deskew data from the delay calculator and uses the deskew data to delay a bit stream on the data channel.