Abstract: Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery latches and instead receiving data from pipeline latches into core logic, the received data mirroring data driven onto the system bus.

Abstract: A data clock recovery system is provided. A phase detector is configured to sample an input data stream by way of a data clock and a second clock to generate a first signal indicating whether a data clock lags or leads a preferred phase of the data clock in relation to an input data stream. A phase controller is configured to process the first signal to shift a phase of the second clock toward a second preferred phase, and to shift a phase of the data clock toward the first preferred phase after the shifting of the phase of the second clock.

Abstract: Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff.

Abstract: Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal, an output latch device that drives data over the data bus in response to an edge of the data clock signal and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock.

Abstract: An apparatus includes termination circuitry to terminate one or more lines. The termination circuitry draws a first current from a termination voltage supply through a termination voltage delivery network for each terminated line carrying a first signal. Partial current shunt circuitry draws a second current from the termination voltage supply through the termination voltage delivery network for each terminated line carrying a second signal. The first and second currents are distinct.

Abstract: One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.

Abstract: An integrated circuit is configured as a selected one of a terminated and a non-terminated bus agent for terminating a bus signal line. Reference level selection logic selects one of a first and a distinct second reference level as a selected level. The integrated circuit compares the bus signal line with the selected level to determine the state of the bus signal line.

Abstract: One or more characteristics of circuitry for an output buffer are identified relative to a reference a plurality of times to produce a sequence of results. One or more compensation signals for one or more output buffers are generated based on results satisfying one or more conditions.

Abstract: A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.

Abstract: Termination circuitry is to terminate one or more lines and is to draw current from a termination voltage supply and through a termination voltage delivery network. Partial termination voltage current shunting may be used to help define a range of current variation through the termination voltage delivery network.