Patents by Inventor Barry B. Arndt

Barry B. Arndt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratio
    Patent number: 9032411
    Abstract: A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Barry B. Arndt, William M. Buros, Jennifer L. Vargus
  • Consolidating CPU - Cache - Memory Access Usage Metrics
    Publication number: 20110161969
    Abstract: A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.
    Type: Application
    Filed: December 25, 2009
    Publication date: June 30, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barry B. Arndt, William M. Buros, Jennifer L. Vargus