Abstract: In a switching circuit, a first electrical element (22) is disabled before a second electrical element (30) is enabled. The switching operation is called break before make and ensures that disabling operation of a first electrical element occurs before enabling operation of a second electrical element. The assurance is in the form of a disable signal being detected from a first electrical element at an input of a first detection circuit (28). Correspondingly, the detected disable signal of the first electrical element enables operation of the second electrical element. Alternatively, a detected disable from the second electrical element at the input of the second detection circuit (20) enables operation of the first electrical element.

Abstract: An output circuit (40) includes pull-up transistor (12), two pull-down transistors (14, 16), and a noise suppression circuit (58). When an input node (50) of the output circuit (40) switches to a logic high voltage, the pull-up transistor (12) is switched off. A first transistor (22) in the noise suppression circuit (58) is switched on, discharges a capacitive load (32) coupled to an output node (60) of the output circuit (40), and charges a capacitor formed by a second transistor (24) in the noise suppression circuit (58). After a time delay, the two pull-down transistors (14, 16) are switched on sequentially and establish two current paths from the output node (60) to ground (25). Then, a third transistor (56) in the noise suppression circuit (58) is switched on, discharges the capacitor (24), and establishes a third current path from the output node (60) to ground.

Abstract: An input circuit (10) includes two inverters (12, 16) and an enable transistor (18). When a logic high enable signal is transmitted to a gate electrode of the enable transistor (18). The two inverters (12, 16) form a latch that holds the data at the input port (21) of the input circuit (10). When a logic low enable signal is transmitted to the gate electrode of the enable transistor (18), the latch formed by the two inverters (12, 16) is disabled, thereby allowing fast data transmission through the input circuit (10). When the voltage at the input port (21) is higher than a supply voltage of the input circuit (10), the enable transistor (18) switches off to protect a voltage supply coupled to the input circuit (10).

Abstract: An ESD protection device and a method for forming the ESD protection device in an active region (13) which is devoid of a field oxide (14). A P type dopant region (22) and an N type dopant region (27) are formed in a semiconductor substrate (11) using photolithographic techniques, wherein they are spaced apart from each other by a spacer region (29). An anode electrode (33) contacts the P type dopant region (22) and a cathode electrode (34) contacts the N type dopant region (27). A parasitic diode resistance of the ESD protection device is governed by the width of the spacer region (29) which, in turn, is governed by the resolution of the photolithographic techniques. Thus, the present invention provides a method for lowering both the parasitic diode resistance and clamp voltage of the ESD protection device which serves to protect integrated circuits from large voltage transients.

Abstract: A mixed mode buffer circuit 11 including a first input (12), a second input (13), and an output (14). A voltage exceeding a supply voltage of mixed mode buffer circuit 11 can be applied to the output (14) without latchup or an increase in leakage current. The mixed mode buffer includes an output transistor (24) of a first conductivity type having a first electrode coupled to the output (14), a control electrode coupled to the first input (12), a second electrode coupled for receiving the supply voltage, and a bulk electrode. A first transistor (19) biases the bulk electrode when the voltage at the output is within a first predetermined range. A first bulk bias circuit (28) biases the bulk electrode when the output voltage is within a second predetermined range. A second bulk bias circuit (27) and a second transistor (18) couples the voltage at the output to the bulk electrode and the control electrode respectively, when the output voltage exceeds the second predetermined range.

Abstract: A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

Abstract: A CMOS multiplexing circuit is provided for selecting one of a plurality of input signals under control of a digital select signal for providing an output signal inverted with respect to the selected input signal. A plurality of processing channels one for each input signal and each having exactly first, second, third and fourth transistors serially connected between first and second sources of operating potential are repsonsive to the digital select signal whereby only the second and third transistors in the selected processing channels are enabled. The other processing channels supporting the remaining input signals are disabled. The first and fourth transistors of the selected processing channel are alternately enabled by one of the plurality of input signals for providing the inverse state thereof at the output formed at the interconnection of the second and third transistors.

Abstract: An integrated voltage regulator is provided that includes an NPN shunt transistor that improves regulation and reduces chip size. A regulator circuit is coupled between an output node and a second supply voltage terminal for biasing an output emitter follower transistor. A voltage divider is coupled between a first supply voltage terminal and the second supply voltage terminal and biases the NPN shunt transistor. The NPN shunt transistor is coupled between the output node and the second supply voltage terminal for shunting excess current from the output node as the voltage on the first supply voltage terminal increases.