Abstract: A composite electrolyte comprises an inorganic clay material and a dielectric solution having a dielectric constant ranging from about 50 to about 85. The composite electrolyte has an ion transference number ranging from about 0.80 to about 1.00. An electrode comprises a component selected from the group consisting of an inorganic clay filler, a polymer, and mixtures thereof. Batteries and electrochemical cells comprising the above composite electrolytes and electrodes are also disclosed.

Abstract: A hydrotherapy pool comprising an enclosure for receiving a patient and for holding a quantity of liquid sufficient for immersing the patient so that the patient receives hydrotherapy, the enclosure having a plurality of openings for facilitating entry and exit from the enclosure; a removable door for each opening; a water tight seal for each door for sealing the door to the enclosure so that water does not leak from the enclosure; and a filling and draining system for filling and draining the enclosure of water. A seating area at a first end of the pool. The pool may have three doors, the doors being disposed with respect to the patient when seated in the seating area facing the patient, to the right of the patient, and to the left of the patient.

Abstract: A system, method, and computer program for managing integrated real-time information about air flight trips and providing that information to multiple users by way of a flight operations system (FOS), including a data engine (DE) and render engine (RE). A computerized Upstream Distribution Center (UDC) containing a packet manager connects to the FOS and to a user interface including a computer display using text, image and color. The UDC is connectable to multiple user interfaces containing copies of the computer program through computer networks by which information is collected and propagated on a real time basis using object-relational mapping, object caching and proactive notification or “push” technology.

Abstract: Disclosed is a SCSI host adapter for use in a computer system. The SCSI host adapter is configured to provide the computer system with interconnection with internal and/or external target devices. The SCSI host adapter includes a low voltage differential connector for interconnecting to a low voltage differential bus, and the low voltage differential bus is configured to communicate a first transaction. The SCSI host adapter also includes a single ended connector for interconnecting to a single ended bus, and the single ended bus is configured to communicate a second transaction. Furthermore, the SCSI host adapter includes a transceiver unit that is configured to interface between the low voltage differential bus and the single ended bus and produce a target information signal. The target information signal is configured to indicate whether the first transaction or the second transaction is occurring between the SCSI host adapter and the low voltage differential bus or the single ended bus.

Abstract: A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

Abstract: A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.

Abstract: A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

Abstract: A system for trapping I/O instructions. The system is comprised of at least one peripheral controller for receiving a plurality of I/O instructions and for initiating trapping of an un-executable I/O instruction by issuing a target abort signal when the peripheral controller senses a power off condition in a peripheral device. A system controller is coupled to the at least one peripheral controller for receiving the target abort signal from the at least one peripheral controller and for sequentially: issuing a system management interrupt (SMI) signal; counting a predetermined time period to allow recognition of the SMI signal; and issuing a cycle completion signal after counting the predetermined time period. A CPU is coupled to the system controller for issuing a plurality of I/O instructions and for receiving the SMI signal and the cycle completion signal from the system controller.

Abstract: An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.

Abstract: An apparatus having a first interface for coupling to a first component bus; a second interface for coupling to a second component bus; an address translation unit coupled to the second interface; and a bus bridge coupled to the first interface and to the second interface.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices.

Abstract: A processor for creating an intelligent input/output subsystems which includes a local processor coupled to a local system bus; a local memory controller coupled to the local system bus that enables access to a memory from the local system bus; a bus bridge having a first bus interface coupled to a first component bus; a second bus interface coupled to a second component bus, the bus bridge including means for creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; and address translation means coupled to the local system bus and the bus bridge for translating addresses between the local system bus and the second component bus.

Abstract: Compounds containing a cephem nucleus are prepared by heating a 1-oxide of a Schiff base of 6-aminopenicillanic acid. These cephem compounds are useful as intermediates in the preparation of physiologically active cephalosporins.