Abstract: A video signal waveform monitor is shown, which receives an input video signal composed of video lines. A video signal digitizer samples the input video signal at video sample points to generate a sequence of video pixel data, which is written into an acquisition framestore is organized into a video pixel array so as to represent a raster of the input video signal. A level analyzer reads the video pixel data row-by-row from segments of the video pixel array and increments video level data at addresses in cache memory in response to the serially-read video pixel data. This generates a sequence of video level data, which is written into an output framestore and which represents the level of the waveform of the input video signal. The segments of the video pixel array comprise at least one and less than all of the columns in the video pixel array.

Abstract: A video signal waveform monitor is shown, which receives an input video signal composed of video lines. A video signal digitizer samples the input video signal at video sample points to generate a sequence of video pixel data, which is written into an acquisition framestore is organized into a video pixel array so as to represent a raster of the input video signal. A level analyzer reads the video pixel data row-by-row from segments of the video pixel array and increments video level data at addresses in cache memory in response to the serially-read video pixel data. This generates a sequence of video level data, which is written into an output framestore and which represents the level of the waveform of the input video signal. The segments of the video pixel array comprise at least one and less than all of the columns in the video pixel array.

Abstract: A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit (401) recovers a clock signal from the test signal and a synchronization circuit generates a synchronized system clock signal from said recovered clock signal. A sinusoid generator (403) generates a sinusoid signal from the synchronized system clock signal and a sampling analog to digital converter (404) samples the sinusoid signal by the recovered clock signal to provide sinusoid samples further comprising: A numerically controlled oscillator (401) is configured to produce sine values and cosine values in response to receiving an input from the system clock signal and a first multiplier (412) is configured to produce a first product of the sinusoid samples and the sine values. In addition, a second multiplier is configured to produce a second product of the sinusoid samples and the cosine values.

Abstract: A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit (401) recovers a clock signal from the test signal and a synchronisation circuit generates a synchronised system clock signal from said recovered clock signal. A sinusoid generator (403) generates a sinusoid signal from the synchronised system clock signal and a sampling analog to digital converter (404) samples the sinusoid signal by the recovered clock signal to provide sinusoid samples further comprising: A numerically controlled oscillator (401) is configured to produce sine values and cosine values in response to receiving an input from the system clock signal and a first multiplier (412) is configured to produce a first product of the sinusoid samples and the sine values. In addition, a second multiplier is configured to produce a second product of the sinusoid samples and the cosine values.

Abstract: A velocity compensator arrangement for a synchronizer which includes an input oscillator, main store and output oscillator in which the controlling voltage of the input oscillator is sampled during one line and compared with the controlling voltage for the next line. Any voltage difference is converted into digital form and this is stored in a digital store until the corresponding line is read out from the main store. The phase of the output oscillator is shifted in dependence on the voltage difference held in the store. This store may comprise part of the main store or be an independent store.

Abstract: A video time base corrector includes an analogue-to-digital converter for converting an incoming analogue video signal to digital form, and a store for receiving successive lines of video information in digital form from the converter. A digital-to-analogue converter converts the digital output signal from the store into analogue form.Control means are provided for writing-in and reading out the digital information into and from the store. A triggered voltage controlled input oscillator determines the rate of conversion of the analogue signal to digital form and the rate of writing into the store. An output oscillator controls the rate of reading out of the digital information from the store and the rate of conversion into analogue form.Sampling means sample the input oscillator controlling voltage during one line and measuring means detect any voltage difference in the controlling voltage during successive lines.

Abstract: A generator system for producing advanced mixed synchronizing pulses and comprising an equalizing pulse detector capable of detecting the presence of a first equalizing pulse of a mixed synchronizing pulse received at its input and a broad pulse generator. Delay means are provided for inhibiting the generation of the broad pulses for a preset period after the detection of the first equalizing pulse. The delay period is less than the period between the first equalizing pulse and the first broad pulse received whereby the broad pulses from the generator are producible in advance of the broad pulses received at the generator input. The generated pulses are added to the original mixed sync. pulse train whereby a mixed sync. pulse train is producible at the generator system output in which the original broad pulses and some of the equalizing pulses are replaced by the generated broad pulses.