Abstract: A circuit with a phase-locked loop circuit which generates audio clock signals with zero ppm error from reference clock signals at a reference frequency is presented. The phase-locked loop (PLL) circuit has a first programmable divider circuit connected to the circuit input terminal, a first fixed divider circuit connected to the PLL output terminal and a second programmable divider circuit connected to the first fixed divider circuit, among other elements. The circuit also has several second fixed divider circuits, each second fixed divider circuit connected to the PLL output terminal, and a multiplexer selectively connecting the second fixed divider circuits to the circuit output terminal responsive to a programmable control signal. By properly selecting the integer divisors for the fixed and programmable divisors, the circuit can generate clock signals at any one of the audio sampling frequencies from a video clock signal.