Abstract: Signal communication paths between multiple chips are established through inter-chip electro-magnetic coupling, thereby potentially eliminating mechanical inter-chip contacts and increasing inter-chip interconnection capacity while maximizing chip real estate allocated to a circuit layer. In one embodiment, multiple chips each include a conductive layer, disposed over a circuit layer on a substrate, divided into electro-magnetic coupling device elements such as capacitor plates. When utilizing capacitor plates, chips are arranged face-to-face with opposing chips having mirror image capacitor plate patterns to form a plurality of capacitors. Conventional signal transmission circuits produce time-varying signals which propagate to conventional signal receiving circuits of another chip via an embodiment of electro-magnetic signal communication paths formed by the capacitors.

Abstract: An extremely compact dynamic memory cell (200) includes a capacitor (204) or any other suitable stored charge device, and a diode (208) such as a Zener diode, a pair of parallel, reverse-connected diodes, or any other suitable voltage dropping device having substantially definite voltage drops when conducting in each direction. The capacitor and Zener diode are connected in series between a Row Select line (202) and a Column Bit line (210). These structures are suitable for fabrication by any of a variety of processes used to fabricate conventional semiconductor DRAMs. The memory cell is replicated millions of times and arrayed in rows and columns as in conventional one-transistor MOSFET DRAM memories to form a memory integrated circuit. Rows of cells are accessed by asserting the corresponding Row Select line, and columns are accessed by asserting the Column Bit line.

Abstract: A memory element that includes a stored charge element coupled to a bi-directional voltage dropping element that exhibits substantially definite voltage drops when conducting in each direction is the basis for a family of memory cells and circuits. An extremely compact dynamic memory cell (200) capable of being stacked includes a capacitor (204) or any other suitable stored charge device, and a voltage dropping element such as a Zener diode (208), a pair of parallel, reverse-connected diodes (910, 920), or any other suitable voltage dropping device having substantially definite voltage drop thresholds when conducting in each direction. Another type of dynamic memory (1000) is read through a transistor (1020) to provide non-destructive reads. Another type of dynamic memory (1200) has column bit lines (1212) that are shared by adjacent cells having memory elements (1230, 1240). An SRAM cell (1300, 1400) is made of a latch (1310) that is accessed through a memory element (1320, 1420).