Abstract: Embodiments of the present invention relate to a floor display system with variable image orientation. Embodiments may further relate to networked data distribution and management; interactivity; image-enhancing optics; controlled audio; a protective covering; an anti-slip feature; fragrance technology; theft prevention; deployment in a track-and-trench system; specialized positioning mechanisms; and lightweight, flexible implementations.

Abstract: Embodiments of the present invention relate to a floor display system with interactive features. The floor display system may be arranged in a public place, and be configured to display electronically modifiable arbitrary content, such as advertising or other informational content. The floor display system may be configured to detect an indication of the presence or activity of a person in the vicinity, and upon detecting the indication, perform a corresponding action in response, such as generating a predetermined display or audio output.

Abstract: Embodiments of the present invention relate to a floor display system with interactive features. The floor display system may be arranged in a public place, and be configured to display electronically modifiable arbitrary content, such as advertising or other informational content. The floor display system may be configured to detect an indication of the presence or activity of a person in the vicinity, and upon detecting the indication, perform a corresponding action in response, such as generating a predetermined display or audio output.

Abstract: A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. A protective bumper attached to the sides of the package provides mechanical shielding for the chip. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: A method of bonding a first plurality of electrical contacts to a second plurality of electrical contacts by aligning the first and second contacts, placing a diaphragm member against the first contacts and applying a differential pressure, such as a vacuum, to the diaphragm in a direction to pull the first contact toward the second contact. Thereafter, the first contacts are bonded to the second contacts with a laser. The diaphragm or a coating on the diaphragm can be a material that absorbs energy from the laser to transfer laser energy to the bond. The diaphragm may be a glass plate or a transparent membrane, may have a support bonded to the first contacts, and may include openings through which the contacts are bonded.

Abstract: A memory circuit in which are stored multiple sets of upper and lower limits that are simultaneously compared with a stream of input data words. The data words and the upper and lower limits may be selectively segmented into data fields or dimensions, and match signals are generated if the input data fields fall within the corresponding fields of the upper and lower limits. The match signals may be selectively masked by a window enable register, and the data fields selected by changing a field length control register.

Abstract: A fast Fourier transform circuit formed on a single chip, including a fast multiplier-accumulator circuit which, in the preferred embodiment, employs a modified form of Booth's algorithm, an adder circuit, a read-only memory for storing FFT twiddle factors, and a random access memory for holding a set of input complex quantities and for receiving intermediate and final results in an in-place FFT operation. In the preferred embodiment, the FFT twiddle factors are stored in Booth's code for greater speed of operation. Control and timing circuitry on the same chip generates control signals and address codes in order to perform a sequence of butterfly computations by repeated use of the multiplier-accumulator and adder circuits, to generate FFT coefficients in the random access memory.