Abstract: A method of forming an output transistor (11) protects the output transistor (11) from overvoltage conditions on an output (13). The body of the output transistor (11) is coupled to the gate of the transistor (11) prior to the high voltage being applied to the output (13).

Abstract: A method of forming an output transistor (11) protects the output transistor (11) from overvoltage conditions on an output (13). The body of the output transistor (11) is coupled to the gate of the transistor (11) prior to the high voltage being applied to the output (13).

Abstract: A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements.