Abstract: A pixel image sensor having an array of pixel elements arranged in a color mosaic pattern, each pixel element being responsive to light of a particular color. Each pixel element is supplied with a reference voltage signal corresponding to the color of light to which the pixel element is responsive. The reference voltage signal determined the sensitivity of the pixel element. The white balance of the image sensor is adjusted by varying independently the reference voltage signals for each color. The color mosaic pattern of the array may include a pixel element responsive to white light. The output from the white pixel sensors may be used to adjust the color constancy of the image sensor. The image array reduces the need for post-capture processing of the image for white balancing, by incorporating the white balance operation into the capture process.

Abstract: A time-integrating pixel sensor having a photo-detector, a capacitor, a comparator and a pixel data buffer. In operation, the photo-current from the photo-detector charges the capacitor and produces a photo-voltage. The photo-voltage sensed by the capacitor and a reference voltage is compared with the comparator. If the photo-voltage exceeds the reference voltage, a global code value is latched into the pixel data buffer. The optical power falling on the photo-detector is determined from the latched code value. An array of sensors is incorporated into a semiconductor device together with circuitry to read and decode the pixel data buffers. The reference voltage may be varied in time to increase the dynamic range of the sensor.

Abstract: A pixel image sensor having an array of pixel elements arranged in a color mosaic pattern, each pixel element being responsive to light of a particular color. Each pixel element is supplied with a reference voltage signal corresponding to the color of light to which the pixel element is responsive. The reference voltage signal determined the sensitivity of the pixel element. The white balance of the image sensor is adjusted by varying independently the reference voltage signals for each color. The color mosaic pattern of the array may include a pixel element responsive to white light. The output from the white pixel sensors may be used to adjust the color constancy of the image sensor. The image array reduces the need for post-capture processing of the image for white balancing, by incorporating the white balance operation into the capture process.

Abstract: A time-integrating pixel sensor having a photo-detector, a capacitor, a comparator and a pixel data buffer. In operation, the photo-current from the photo-detector charges the capacitor and produces a photo-voltage. The photo-voltage sensed by the capacitor and a reference voltage is compared with the comparator. If the photo-voltage exceeds the reference voltage, a global code value is latched into the pixel data buffer. The optical power falling on the photo-detector is determined from the latched code value. An array of sensors is incorporated into a semiconductor device together with circuitry to read and decode the pixel data buffers. The reference voltage may be varied in time to increase the dynamic range of the sensor.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.

Abstract: A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.

Abstract: A current mirror (100) has an input stage (104) and an output stage (106), both preferably employing FET's. (Field Effect Transistors) An amplifier (102) equalizes drain-to-source voltages between FET's in the input and output stages to provide a higher output impedance. A resistance (R1), coupled in series with an FET in the output stage (106), provides degenerative feedback. A reference current generator (400) is constructed of two such current mirrors, one being the compliment of the other, to provide one or more stable reference currents. Loop gain of the reference current generator (400) is greater than one at start-up, but degenerative feedback reduces the loop gain to one at a predetermined stable operating point.

Abstract: A voltage track and hold circuit operates to track a tuning voltage and holding the tuning voltage (404) as a reference voltage (408). In the track mode, the track and hold circuit includes a first operational transconductance amplifier (401) and a first charge storage device (402) coupled to a first input (403) of the first operational transconductance amplifier (401). The first charge storage device (402) accumulates a charge that corresponds with the tuning voltage (404). A second charge storage device (405) is coupled to a second input (406) and an output (407) of the first operational transconductance amplifier (401). The second charge storage device (405) accumulates a reference charge such that the reference voltage (408) present at the second charge storage device (405) is substantially equivalent to the tuning voltage (404).

Abstract: A radio receiver has a receiver section (103) that receives an information signal and an integrated circuit (105) in which a default operating condition of an electronic device is selectively programmed. A mask option programming link in the integrated circuit (105) is programmed while maintaining electrical isolation of a programming bias from the electronic device (207). The mask option programming link has a first conductor (211) in a first layer with first (212) and second (213) programming contact terminals. A second conductor (210) that determines a default operating condition of the electronic device (207), resides in a second layer that is electrically isolated from the first layer. When sufficient programming bias is applied to the programming terminals of the first conductor (211), energy dissipated by the first conductor eliminates coupling of the second conductor (210) to the electronic device (207), changing its default operating condition.