Abstract: A diagnostic system for a large, multiple processor data processing system. Diagnostic access between dual diagnostic intelligent consoles and each processor is provided through a diagnostic network of communication links and switching nodes which are independent of normal data processing system communication channels. The diagnostic network consists of two embedded three structure communication networks providing two different diagnostic communication paths to each processor within the data processing system.

Abstract: A data processing system including an addressable main memory for storing data and directly executable microinstructions, and a central processing chip having a data interface terminal and an instruction terminal. A processor memory bus is connected between the main addressable memory and the central processing chip data interface terminal. An instruction bus is connected between the central processing chip instruction terminal and the addressable memory.The directly executable microinstructions in the addressable main memory are fetched from the main memory by an apparatus which includes an instruction address circuit connected to the processor memory bus and the instruction bus. The instruction address circuit includes a virtual address register circuit for receiving a portion of a virtual address from the instruction bus, and a portion of the mentioned virtual address from the processor memory bus.