Patents by Inventor Barry L. Minor
Barry L. Minor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9501809Abstract: A graphics client receives a frame, the frame comprising scene model data. A server load balancing factor is set based on the scene model data. A prospective rendering factor is set based on the scene model data. The frame is partitioned into a plurality of server bands based on the server load balancing factor and the prospective rendering factor. The server bands are distributed to a plurality of compute servers. Processed server bands are received from the compute servers. A processed frame is assembled based on the received processed server bands. The processed frame is transmitted for display to a user as an image.Type: GrantFiled: February 21, 2016Date of Patent: November 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joaquin Madruga, Barry L. Minor, Mark R. Nutter
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Patent number: 9483864Abstract: Scene model data, including a scene geometry model and a plurality of pixel data describing objects arranged in a scene, is received. A primary pixel color and a primary ray are generated based on a selected first pixel data. If the primary ray intersects an object in the scene, an intersection point is determined. A surface normal is determined based on the object intersected and the intersection point. The primary pixel color is modified based on a primary hit color, determined based on the intersection point. A plurality of ambient occlusion (AO) rays each having a direction, D, are generated based on the intersection point, P and the surface normal. Each AO ray direction is reversed and the AO ray origin is set to a point outside the scene. An AO ray that does not intersect an object before reaching the intersection point is included in ambient occlusion calculations.Type: GrantFiled: December 5, 2008Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark R. Nutter, Joaquin Madruga, Barry L. Minor
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Publication number: 20160171643Abstract: A graphics client receives a frame, the frame comprising scene model data. A server load balancing factor is set based on the scene model data. A prospective rendering factor is set based on the scene model data. The frame is partitioned into a plurality of server bands based on the server load balancing factor and the prospective rendering factor. The server bands are distributed to a plurality of compute servers. Processed server bands are received from the compute servers. A processed frame is assembled based on the received processed server bands. The processed frame is transmitted for display to a user as an image.Type: ApplicationFiled: February 21, 2016Publication date: June 16, 2016Inventors: Joaquin Madruga, Barry L. Minor, Mark R. Nutter
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Patent number: 9270783Abstract: A graphics client receives a frame, the frame comprising scene model data. A server load balancing factor is set based on the scene model data. A prospective rendering factor is set based on the scene model data. The frame is partitioned into a plurality of server bands based on the server load balancing factor and the prospective rendering factor. The server bands are distributed to a plurality of compute servers. Processed server bands are received from the compute servers. A processed frame is assembled based on the received processed server bands. The processed frame is transmitted for display to a user as an image.Type: GrantFiled: December 6, 2008Date of Patent: February 23, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joaquin Madruga, Barry L. Minor, Mark R. Nutter
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Patent number: 9053069Abstract: A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail pointers of a shared buffer region when the devices perform operations on the shared buffer region using signal notification channels of the devices. Thus, when a producer device that produces data to the shared buffer region writes data to the shared buffer region, an update to the head pointer is written to a signal notification channel of a consumer device. When a consumer device reads data from the shared buffer region, the consumer device writes a tail pointer update to a signal notification channel of the producer device. In addition, channels may operate in a blocking mode so that the corresponding device is kept in a low power state until an update is received over the channel.Type: GrantFiled: August 23, 2012Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Daniel A. Brokenshire, Charles R. Johns, Mark R. Nutter, Barry L. Minor
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Patent number: 9038079Abstract: A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.Type: GrantFiled: September 15, 2012Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Benjamin Gale Alexander, Gregory Howard Bellows, Joaquin Madruga, Barry L. Minor
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Patent number: 8949529Abstract: Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, each of multiple memory objects can be populated with work items and can be associated with attributes that can include information which can be used to describe data of each memory object and/or which can be used to process data of each memory object. The attributes can be used to indicate one or more of a cache policy, a cache size, and a cache line size, among others. In one or more embodiments, the attributes can be used as a history of how each memory object is used. The attributes can be used to indicate cache history statistics (e.g., a hit rate, a miss rate, etc.).Type: GrantFiled: December 30, 2009Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Gregory H. Bellows, Joaquin Madruga, Ross A. Mikosh, Barry L. Minor
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Patent number: 8903180Abstract: A mechanism is provided for security screening image analysis simplification through object pattern identification. Popular consumer electronics and other items are scanned in a control system, which creates an electronic signature for each known object. The system may reduce the signature to a hash value and place each signature for each known object in a “known good” storage set. For example, popular mobile phones, laptop computers, digital cameras, and the like may be scanned for the known good signature database. At the time of scan, such as at an airport, objects in a bag may be rotated to a common axis alignment and transformed to the same signature or hash value to match against the known good signature database. If an item matches, the scanning system marks it as a known safe object.Type: GrantFiled: September 12, 2012Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Joaquin Madruga, Barry L. Minor, Michael A. Paolini
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Patent number: 8893145Abstract: A method efficiently dispatches completes a work element within a multi-node, data processing system that has a global command queue (GCQ) and at least one high latency node. The method comprises: at the high latency processor node, work scheduling logic establishing a local command/work queue (LCQ) in which multiple work items for execution by local processing units can be staged prior to execution; a first local processing unit retrieving via a work request a larger chunk size of work than can be completed in a normal work completion execution cycle by the local processing unit; storing the larger chunk size of work retrieved in a local command/work queue (LCQ); enabling the first local processing unit to locally schedule and complete portions of the work stored within the LCQ; and transmitting a next work request to the GCQ only when all the work within the LCQ has been dispatched by the local processing units.Type: GrantFiled: September 15, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Benjamin Gale Alexander, Gregory Howard Bellows, Joaquin Madruga, Barry L. Minor
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Patent number: 8868844Abstract: A method for implementing a software-managed cache comprises determining an object identifier (ID) for each of a first set of objects of a plurality of objects resident in a local memory, to generate a first cache table, the first cache table comprising a plurality of entries. Each object comprises an object ID and an effective address. The method receives a request for an object, the request comprising an object ID. The method compares the received object ID with the entries in the first cache table. In the event the received object ID matches an entry in the first cache table, the method returns the matching entry in response to the request. In the event the received object ID does not match an entry in the first cache table, the method calculates an effective address in the local memory of the object associated with the object ID.Type: GrantFiled: June 25, 2008Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Mark Richard Nutter, Dean Joseph Burdick, Barry L. Minor
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Patent number: 8862827Abstract: A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effective address matches the requested effective address, the cache manager identifies a corresponding cache location and retrieves the data from the identified cache location. However, when the most recently used effective address fails to match the requested effective address, the cache manager determines whether the requested effective address matches a subsequent effective address stored in the mapped tag vector. When the cache manager determines a match to a subsequent effective address, the cache manager identifies a different cache location corresponding to the subsequent effective address and retrieves the data from the different cache location.Type: GrantFiled: December 29, 2009Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Brian Flachs, Barry L. Minor, Mark Richard Nutter
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Patent number: 8819690Abstract: A system for efficient dispatch/completion of a work element within a multi-node data processing system. The system comprises a processor performing the functions of: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.Type: GrantFiled: December 30, 2009Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Benjamin G. Alexander, Gregory H. Bellows, Joaquin Madruga, Barry L. Minor
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Patent number: 8665271Abstract: A method comprises receiving scene model data including a scene geometry model and a plurality of pixel data describing objects arranged in a scene. The method generates a primary ray based on a selected first pixel data. In the event the primary ray intersects an object in the scene, the method determines primary hit color data and generates a plurality of secondary rays. The method groups the secondary packets and arranges the packets in a queue based on the octant of each direction vector in the secondary ray packet. The method generates secondary color data based on the secondary ray packets in the queue and generates a pixel color based on the primary hit color data, and the secondary color data. The method generates an image based on the pixel color for the pixel data.Type: GrantFiled: April 27, 2012Date of Patent: March 4, 2014Assignee: International Business Machines CorporationInventors: Mark Richard Nutter, Gordon C. Fossum, Joaquin Madruga, Barry L. Minor
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Patent number: 8640109Abstract: A method for managing hardware resources and threads within a data processing system is disclosed. Compilation attributes of a function are collected during and after the compilation of the function. The pre-processing attributes of the function are also collected before the execution of the function. The collected attributes of the function are then analyzed, and a runtime configuration is assigned to the function based of the result of the attribute analysis. The runtime configuration may include, for example, the designation of the function to be executed under either a single-threaded mode or a simultaneous multi-threaded mode. During the execution of the function, real-time attributes of the function are being continuously collected. If necessary, the runtime configuration under which the function is being executed can be changed based on the real-time attributes collected during the execution of the function.Type: GrantFiled: April 11, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Gregory H. Bellows, Brian H. Horton, Joaquin Madruga, Barry L. Minor
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Patent number: 8640108Abstract: A technique for managing hardware resources and threads within a data processing system is disclosed. Compilation attributes of a function are collected during and after the compilation of the function. The pre-processing attributes of the function are also collected before the execution of the function. The collected attributes of the function are then analyzed, and a runtime configuration is assigned to the function based of the result of the attribute analysis. The runtime configuration may include, for example, the designation of the function to be executed under either a single-threaded mode or a simultaneous multi-threaded mode. During the execution of the function, real-time attributes of the function are being continuously collected. If necessary, the runtime configuration under which the function is being executed can be changed based on the real-time attributes collected during the execution of the function.Type: GrantFiled: December 31, 2009Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Greg H. Bellows, Brian H. Horton, Joaquin Madruga, Barry L. Minor
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Patent number: 8572622Abstract: A system efficiently dispatches/completes a work element within a multi-node, data processing system that has a global command queue (GCQ) and at least one high latency node. The system comprises: at the high latency processor node, work scheduling logic establishing a local command/work queue (LCQ) in which multiple work items for execution by local processing units can be staged prior to execution; a first local processing unit retrieving via a work request a larger chunk size of work than can be completed in a normal work completion/execution cycle by the local processing unit; storing the larger chunk size of work retrieved in a local command/work queue (LCQ); enabling the first local processing unit to locally schedule and complete portions of the work stored within the LCQ; and transmitting a next work request to the GCQ only when all the work within the LCQ has been dispatched by the local processing units.Type: GrantFiled: December 30, 2009Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Benjamin G. Alexander, Gregory H. Bellows, Joaquin Madruga, Barry L. Minor
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Patent number: 8549521Abstract: An approach is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.Type: GrantFiled: March 14, 2008Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Daniel Alan Brokenshire, Michael Norman Day, Barry L Minor, Mark Richard Nutter
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Publication number: 20130254776Abstract: A method efficiently dispatches/completes a work element within a multi-node, data processing system that has a global command queue (GCQ) and at least one high latency node. The method comprises: at the high latency processor node, work scheduling logic establishing a local command/work queue (LCQ) in which multiple work items for execution by local processing units can be staged prior to execution; a first local processing unit retrieving via a work request a larger chunk size of work than can be completed in a normal work completion/execution cycle by the local processing unit; storing the larger chunk size of work retrieved in a local command/work queue (LCQ); enabling the first local processing unit to locally schedule and complete portions of the work stored within the LCQ; and transmitting a next work request to the GCQ only when all the work within the LCQ has been dispatched by the local processing units.Type: ApplicationFiled: September 15, 2012Publication date: September 26, 2013Applicant: IBM CORPORATIONInventors: Benjamin G. Alexander, Gregory H. Bellows, Joaquin Madruga, Barry L. Minor
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Patent number: 8525826Abstract: A method comprises receiving scene model data including a scene geometry model and a plurality of pixel data describing objects arranged in a scene. The method generates a primary ray based on a selected first pixel data. In the event the primary ray intersects an object in the scene, the method determines primary hit color data and generates a plurality of secondary rays. The method groups the secondary packets and arranges the packets in a queue based on the octant of each direction vector in the secondary ray packet. The method generates secondary color data based on the secondary ray packets in the queue and generates a pixel color based on the primary hit color data, and the secondary color data. The method generates an image based on the pixel color for the pixel data.Type: GrantFiled: August 8, 2008Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Mark Richard Nutter, Gordon C. Fossum, Joaquin Madruga, Barry L. Minor
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Patent number: 8516461Abstract: A method provides efficient dispatch/completion of an N Dimensional (ND) Range command in a data processing system (DPS). The method comprises: a compiler generating one or more commands from received program instructions; ND Range work processing (WP) logic determining when a command generated by the compiler will be implemented over an ND configuration of operands, where N is greater than one (1); automatically decomposing the ND configuration of operands into a one (1) dimension (1D) work element comprising P sequentially ordered work items that each represent one of the operands; placing the 1D work element within a command queue of the DPS; enabling sequential dispatching of 1D work items in ordered sequence from to one or more processing units; and generating an ND Range output by mapping the 1D work output result to an ND position corresponding to an original location of the operand represented by the 1D work item.Type: GrantFiled: September 15, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Gregory Howard Bellows, Brian H. Horton, Joaquin Madruga, Barry L. Minor