Abstract: An apparatus and method for identifying faults in a digital logic circuit system combines the output of a feedback signature generator and a synchronous transition counter to provide a unique signature sensitive both to bit pattern timing and bit pattern sequence. A plurality of output signals of the circuit system produced in response to a preselected input signal pattern is processed synchronously through a feedback signature generator or feedback shift register network, such as a serial cyclic redundancy check (CRC) network, and a synchronous bit transition counting network. A preselected portion of the output of the bit transition counting network is combined with a preselected portion of the bits of the shift register network to obtain a pseudo-random characteristic output bit pattern, or signature, which is unique to the circuit system under test. The fault detecting capability approaches 100 percent with an imbedded indication of the input test pattern duration as verification.

Abstract: A device for testing the logic states of integrated circuits while operating in-circuit. The device includes a hand-held housing containing a pair of spaced circuit boards to which a clip is electrically coupled, the clip having terminals for making electrical contact with the pins on a test IC. The device has a circuit programmed for a particular IC by a socket having removable pins of different lengths. The socket has means for receiving a reference IC against which the test IC is to be compared. Switch means coupled with the circuit permit individual testing of the pins of the test IC.