Abstract: A controller associated with a network connection includes a high speed local interface and a high overhead system interface. The controller can be a power controller for a power over Ethernet application. A controller for each connection is interconnected through the high speed interface. One of the controllers is configured at an address in the high overhead system interface to permit control instructions to be directed to the interconnected controllers from the host system. The architecture avoids the high overhead and complexity associated with multiple devices on the high overhead system interface and distributes processing and thermal loads among the controllers. The controller connected to the high overhead system interface can address the other controllers simply and rapidly to obtain a distributed control system for controlling power over network connections. The architecture reduces pin count, distributes thermal loads, reduces area requirements, and provides a flexible control solution.

Abstract: Devices, systems, and methods for providing an on-chip, temperature-stable resistance network for generating a precision current or precision resistance are disclosed. The resistance network includes a first resistance material having a linear, negative temperature coefficient of resistance and a second resistance material having a linear, positive temperature resistance. The first and second resistance materials are arrayed in segments proximate to a local, pulsed thermal gradient and are combined or mixed, i.e., trimmed, to provide a zero or near zero thermal coefficient.

Abstract: A method for characterizing a load on a data line includes the steps of: (A) Applying at least three successive voltages to the data line. Each respective odd-numbered successive voltage of the at least three successive voltages has substantially a first voltage value displaced a first voltage interval from a reference voltage value. Each respective even-numbered successive voltage of the at least three successive voltages has substantially a second voltage value displaced a second voltage interval from the reference voltage value. (B) Measuring a respective current value on the data line while each of the at least three successive voltages is applied to the data line. (C) Comparing the respective current values for selected successive voltages of the at least three successive voltages to determine whether a hysteric impedance change occurs when voltage on the data line is varied.

Abstract: A digital-to-analog converter having a compact “M-2M” binary-weighted ladder structure, where “M” represents an effective resistance inversely proportional to the W/L line ratio of an n-type or p-type metal oxide semiconductor (MOS) device. A reduction in the number of ladder components is accomplished by utilizing the MOS device's inherent switching function in combination with the device's resistive behavior. The ladder is comprised of a plurality of “2M” rungs, one rung for each binary bit, and each rung is comprised of a complementary pair of upper and lower MOS devices series-connected at a common node. Each device in the pair has an effective resistance of 2M ohms and only one is enabled at any given time depending upon the value of the associated binary bit. Permanently enabled MOS devices having an effective resistance of M ohms and interconnecting the common nodes of adjacent binary bit device pairs make up an “M” runner.

Abstract: A non-volatile memory cell comprising a metal oxide semiconductor field effect transistor (MOSFET) fabricated to read back a logic level “one” state and programmable by a gate to drain fusing to read back to a logic level “zero” state. The drain is patterned to enhance the formation of a localized hot spot during device lateral NPN transistor snapback for a controlled meltdown of gate oxide and the creation of an ohmic gate to drain path. A metal oxide semiconductor (MOS) integrated circuit typically includes a plurality of memory cells composing a programmable array. The drains of each memory cell are tied together in parallel and connected to a high-level programming voltage, and the sources are tied to ground.

Abstract: A motor controller controls motor rotational speed by repeatedly executing a sequence of operations. Initially, a pulse is generated that causes a predetermined fixed current to be supplied to the motor winding for a predetermined driving interval. The winding current is forced to zero after the pulse has occurred. A settling interval is allowed to pass in which the back EMF across the motor winding stabilizes, and then the winding back EMF is compared to a velocity command voltage representing the desired rotational speed of the motor. If at the end of the settling interval the back EMF is less than the velocity command voltage, indicating that the motor speed is less than the desired speed, then a new control cycle is begun, starting with the assertion of the current-driving pulse.

Abstract: A motor controller controls a motor's rotational speed using sensed back electromagnetic force (back EMF) of the motor. The sensed back EMF is presumed to contain an error component caused by series resistance in the motor coil. A velocity sense signal is continually generated representing the sum of the measured back EMF and an error-cancelling quantity equal to the current in the coil scaled according to a gain-control signal stored in the controller. During the first part of a calibration operation, the coil current is set to zero until a time T.sub.1 at which the coil current is substantially zero and the motor velocity is substantially constant. The value of the velocity sense signal is stored at the time T.sub.1, this value representing the zero-current back EMF of the coil.

Abstract: Signal conditioning circuitry for a three plate capacitive pressure transducer eliminates the effects of parasitic capacitance in the transducer's output, to provide a true indication of sensed pressure magnitude as an electrical signal equivalent of the instantaneous value of only the pressure responsive capacitance of the transducer.