Abstract: A system for processing sub-blocks of a macroblock of a video frame. In an example embodiment, the system includes a first module that is adapted to process each sub-block of the macroblock, wherein each sub-block is associated with a predetermined position in a first sequence. The processing of certain sub-blocks in the first sequence requires results of processing of one or more previously processed sub-blocks in the first sequence. A controller selectively enables the first module to process each sub-block of a second sequence that is altered from the first sequence so that the first module implements parallel or pipelined processing of certain sub-blocks of the macroblock. In a more specific embodiment each sub-block in the first sequence of sub-blocks is consecutively numbered 0-15 according to H.264 standards.

Abstract: A system for selectively handling information. In an example embodiment, the system includes a first mechanism for processing information pertaining to one or more sub-blocks of a macroblock in a first stream and a second stream, and outputting a first processed stream and a second processed stream in response thereto. A second mechanism selectively combines information in the first processed stream and the second processed stream and provides an updated version of the first stream or the second stream to the first mechanism in response thereto. In a more specific embodiment, the first mechanism includes a processor, such as in intra 4×4 search, module, that processes a sub-block of a macroblock by performing intra prediction for the sub-block. The processor is adapted to process sub-blocks of a macroblock in parallel, such as in a pipelined fashion or via separate engines capable of operating in parallel.

Abstract: A system for processing sub-blocks of a macroblock of a video frame. In an example embodiment, the system includes a first module that is adapted to process each sub-block of the macroblock, wherein each sub-block is associated with a predetermined position in a first sequence. The processing of certain sub-blocks in the first sequence requires results of processing of one or more previously processed sub-blocks in the first sequence. A controller selectively enables the first module to process each sub-block of a second sequence that is altered from the first sequence so that the first module implements parallel or pipelined processing of certain sub-blocks of the macroblock. In a more specific embodiment each sub-block in the first sequence of sub-blocks is consecutively numbered 0-15 according to H.264 standards.

Abstract: A system for selectively handling information. In an example embodiment, the system includes a first mechanism for processing information pertaining to one or more sub-blocks of a macroblock in a first stream and a second stream, and outputting a first processed stream and a second processed stream in response thereto. A second mechanism selectively combines information in the first processed stream and the second processed stream and provides an updated version of the first stream or the second stream to the first mechanism in response thereto. In a more specific embodiment, the first mechanism includes a processor, such as in intra 4×4 search, module, that processes a sub-block of a macroblock by performing intra prediction for the sub-block. The processor is adapted to process sub-blocks of a macroblock in parallel, such as in a pipelined fashion or via separate engines capable of operating in parallel.

Abstract: A dual function interface operating in a Personal Computer Memory Card International Association (PCMCIA) mode of operation switches to an alternative interface operating in the appropriate mode of operation as defined by the alternative interface system specification. This is accomplished by setting a unique combination of address lines (203) and/or control lines (202) and automatically and transparently switching from the PCMCIA mode of operation to the alternate mode operation in response to the unique combination.

Abstract: A PCMCIA card having independent functionality and alternatively arranged to operate in conjunction with a host computer, that includes a peripheral apparatus (109) having an integral CPU (125), a power source (129), and a power supply (127) for exhibiting an independent operating state; and an interface function (121) integral with and coupled to said peripheral apparatus (109), said interface function arranged and constructed to couple said peripheral apparatus to the host computer (101) over a PCMCIA compliant interface and initiate a dependent operating state at said peripheral apparatus (109).

Abstract: A peripheral card (109) having an adaptive PCMCIA compliant interface including either an adaptive card present or card configuration function that includes a peripheral apparatus (209) arranged and constructed to operate in conjunction with a host computer (101) over a PCMCIA compliant interface, and an interface logic (205), coupled to the peripheral apparatus (209) and to a PCMCIA peripheral port (201), for interfacing the peripheral apparatus to the PCMCIA peripheral port (201), the interface logic further adaptively providing a card present signal at the PCMCIA peripheral port (201) when the peripheral apparatus (209) and the interface logic (205) expects the PCMCIA peripheral port (201) to be activated by the host computer (101) or alternatively adaptively providing configuration information pertaining to the peripheral apparatus to the host computer.

Abstract: An interface device (102) and corresponding method for coupling a peripheral controller (117) to a host computer (100), the interface device including an emulated universal asynchronous receiver transmitter (UART) (113) for the host computer. The interface device further includes a plurality of registers (203), preferably a control (215), status (227), and data register, such as a multi-register data buffer (401), corresponding to the registers of a UART, a host computer port (112), preferably compatible with a PCMCIA standard, that includes an address map for the plurality of registers (203), a peripheral controller port (114) providing an address mapped parallel interface to the plurality of registers (203), and control logic (207) for providing status signals, including UART status signals, to the host computer port and to the peripheral controller port.

Abstract: A pulse controller for controlling the current supply to a plurality of d.c. loads through a respective main thyristor for each load is provided with digital circuitry operable to maintain the mark-space ratios of voltage applied to the loads in a relationship to one another which is set by a differential control circuit while the mark-space ratios are simultaneously varied in response to a drive control circuit. The controller may be used to control two d.c. motors respectively driving right-hand and left-hand traction wheels of a battery-electric vehicle, to provide differential drive when the vehicle negotiates a curve.