Abstract: Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Abstract: Apparatus and methods are disclosed, such as those involving a high frequency transmitter. One such apparatus includes a pre-amplifier configured to receive an input signal via an input node; and a capacitor block electrically coupled between the pre-amplifier and an output node from which an output signal is transmitted. The capacitor block is configured to provide charge to the output node or pull charge from the output node while the output signal transitions. The apparatus further includes a switch electrically coupled between the output node and a voltage reference, wherein the switch is turned on or off at least partly in response to a signal from the pre-amplifier. This configuration effectively reduces rise and fall time of the output signal for high-frequency transmission.

Abstract: Apparatus and methods are disclosed, such as those involving a high frequency transmitter. One such apparatus includes a pre-amplifier configured to receive an input signal via an input node; and a capacitor block electrically coupled between the pre-amplifier and an output node from which an output signal is transmitted. The capacitor block is configured to provide charge to the output node or pull charge from the output node while the output signal transitions. The apparatus further includes a switch electrically coupled between the output node and a voltage reference, wherein the switch is turned on or off at least partly in response to a signal from the pre-amplifier. This configuration effectively reduces rise and fall time of the output signal for high-frequency transmission.

Abstract: A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control unit, a one-time programmable memory, a charge pump and a switching network. The control unit is to receive an operating state. The charge pump is connected to a first voltage and configured to generate a second voltage using the first voltage. The control unit activates the charge pump based upon the received operating state. The one-time programmable memory is connected to the charge pump via a switching network. The switching network is configured by the control unit to provide a voltage required by the received operating state to the one-time programmable memory.

Abstract: Signals, such as the +5V signal, the HPD signal, and LOS output from DDC, CEC, or HDMI signals are dynamically monitored, whereby a stand-by mode is entered in the absence of signal activity in any of the above-mentioned dynamically monitored signals. Such a monitoring architecture reduces power dissipation and allows the realization of low-power source/sink architectures.

Abstract: A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.