Patents by Inventor Barry Watson
Barry Watson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10987676Abstract: Screens for conical mills and an improved gearbox and housing for such conical mills are shown and described. The screens are frusto-conically-shaped and include a tapered sidewall with a plurality of openings in the sidewall that may be of uniform size. Each opening is separated from adjacent openings by spacing distances which are shorter at the top of the tapered sidewall and longer at the bottom of the tapered sidewall to thereby reduce the residence time of the powder being milled at the top of the tapered sidewall and to increase the residence time of the powder being milled at the bottom of the tapered sidewall.Type: GrantFiled: July 12, 2016Date of Patent: April 27, 2021Assignee: Quadro Engineering Corp.Inventors: Wilf Sanguesa, Barry Watson, Jeff Verberne, Sean Watson
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Publication number: 20190009278Abstract: Screens for conical mills and an improved gearbox and housing for such conical mills are shown and described. The screens are frusto-conically-shaped and include a tapered sidewall with a plurality of openings in the sidewall that may be of uniform size. Each opening is separated from adjacent openings by spacing distances which are shorter at the top of the tapered sidewall and longer at the bottom of the tapered sidewall to thereby reduce the residence time of the powder being milled at the top of the tapered sidewall and to increase the residence time of the powder being milled at the bottom of the tapered sidewall.Type: ApplicationFiled: July 12, 2016Publication date: January 10, 2019Applicant: QUADRO ENGINEERING CORP.Inventors: Wilf SANGUESA, Barry WATSON, Jeff VERBERNE, Sean WATSON
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Patent number: 7150199Abstract: An improved strain gage and an improved manufacturing method are disclosed. The strain gage includes a semi-rigid substrate having a thickness of 3 to 30 mils, a resistive strain sensitive foil bonded to the semi-rigid substrate for providing a resistance varying with strain associated with a surface to which the strain gage is attached, a first and a second terminal operatively connected to the resistive strain sensitive foil, and an anti-static layer. The improved strain gage allows for reduced labor content in manufacturing by allowing use of modern automated electronic component manufacturing equipment.Type: GrantFiled: October 5, 2004Date of Patent: December 19, 2006Assignee: Vishay Intertechnology, Inc.Inventors: Thomas Patrick Kieffer, Robert Barry Watson, Sharon Lee Karcher Harris
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Publication number: 20040229977Abstract: Low haze or transparent thermoplastic polyolefinic resins have at least one colorant or pigment uniformly distributed therein. The compositions contain a polypropylene material and a second polyolefin comprising copolymer or homopolymer of ethylene or butene. The compositions can be formed into useful mold-in color panel for automotive and other use.Type: ApplicationFiled: November 13, 2003Publication date: November 18, 2004Inventors: Barry Watson, Perry J. Palanca, Kenneth C. English, Kris W. Winowiecki
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Publication number: 20040159162Abstract: An improved strain gage is disclosed. The strain gage includes a semi-rigid substrate having a thickness of about 1 to about 30 mils, a resistive strain sensitive foil bonded to the semi-rigid substrate for providing a resistance varying with strain associated with a surface to which the strain gage is attached, and a first and a second terminal operatively connected to the resistive strain sensitive foil.Type: ApplicationFiled: February 19, 2003Publication date: August 19, 2004Applicant: Vishay IntertechnologyInventors: Thomas Patrick Kieffer, Robert Barry Watson, Sharon Lee Karcher Harris
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Patent number: 6477258Abstract: A transducer assembly for use with an apparatus comprising a sound transmitting earpiece comprises a sound transmitting element (1) adapted to be worn between such an earpiece and the ear, a sound transducer (3), to be located remote from the earpiece and a hollow tube (2) for acoustically coupling the sound transmitting element (1) to the transducer (3).Type: GrantFiled: June 23, 2000Date of Patent: November 5, 2002Inventors: Michael Barry Watson, Richard Herman
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Patent number: 6219758Abstract: A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception.Type: GrantFiled: March 25, 1998Date of Patent: April 17, 2001Assignee: International Business Machines CorporationInventors: Jennifer Almoradie Navarro, Barry Watson Krumm, Chung-Lung Kevin Shum, Pak-kin Mak, Michael Fee
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Patent number: 6119219Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.Type: GrantFiled: April 30, 1998Date of Patent: September 12, 2000Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Dean G. Bair, Mark Steven Farrell, Barry Watson Krumm, Pak-kin Mak, Jennifer Almoradie Navarro, Timothy John Slegel
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Patent number: 6105109Abstract: SMP computers systems can add to the first level cache a fill mode latch and achieve straightforward, high-performance loading of a writable cache code array that is part of a hierarchical cache structure.A new code array's write control elements include a control latch called "fill mode" for the BCE controls which when fill mode is active, then a disable is also active, since reads of the code array may not give accurate data when the array is not yet filled-up/fully valid. New mode follows the sequential steps which process code by:a) purge the cache array; thenb) disable the code array; thenc) turn on fill mode with a buffer control element fill mode latch; and then processd) code increments once through a range of line addresses, where the range is at least as wide as the range(s) specified in the code array's lookup mechanism.e) turn off fill mode; thenf) purge the cache array again: and theng) enable the code array (turn off the code array disable bit).h) resume normal operation to end the sequence.Type: GrantFiled: February 19, 1998Date of Patent: August 15, 2000Assignee: International Business Machines CorporationInventors: Barry Watson Krumm, Charles Franklin Webb, Timothy John Slegel, Mark Steven Farrell, Yuen Hung Chan
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Patent number: 6079013Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.Type: GrantFiled: April 30, 1998Date of Patent: June 20, 2000Assignee: International Business Machines CorporationInventors: Charles Franklin Webb, Dean G. Bair, Mark Steven Farrell, Barry Watson Krumm, Pak-kin Mak, Jennifer Almoradie Navarro, Timothy John Slegel
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Patent number: 6035392Abstract: A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, thType: GrantFiled: February 20, 1998Date of Patent: March 7, 2000Assignee: International Business Machines CorporationInventors: John Stephen Liptay, Mark Anthony Check, Barry Watson Krumm, Jennifer Almoradie Navarro, Charles Franklin Webb
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Patent number: 6026488Abstract: A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, thType: GrantFiled: February 20, 1998Date of Patent: February 15, 2000Assignee: International Business Machines CorporationInventors: John Stephen Liptay, Mark Anthony Check, Barry Watson Krumm, Jennifer Almoradie Navarro, Charles Franklin Webb
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Patent number: 5819078Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.Type: GrantFiled: June 10, 1997Date of Patent: October 6, 1998Assignee: International Business Machines CorporationInventors: Mark Steven Farrell, Barry Watson Krumm, Jennifer Serena Almoradie Navarro, Charles Franklin Webb
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Patent number: 5713035Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.Type: GrantFiled: March 31, 1995Date of Patent: January 27, 1998Assignee: International Business Machines CorporationInventors: Mark Steven Farrell, Barry Watson Krumm, John Stephen Liptay, Charles Franklin Webb, Steven QiHong Ying
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Patent number: 5684975Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.Type: GrantFiled: May 30, 1995Date of Patent: November 4, 1997Assignee: International Business Machines CorporationInventors: Karl Jean Duvalsaint, Mark Steven Farrell, Barry Watson Krumm, Donald William McCauley, Charles Franklin Webb
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Patent number: 5680598Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.Type: GrantFiled: March 31, 1995Date of Patent: October 21, 1997Assignee: International Business Machines CorporationInventors: Mark Steven Farrell, Barry Watson Krumm, Jennifer Serena Almoradie Navarro, Charles Franklin Webb
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Patent number: 5652853Abstract: A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).Type: GrantFiled: May 31, 1995Date of Patent: July 29, 1997Assignee: International Business Machines CorporationInventors: Karl Jean Duvalsaint, Peter Hermon Gum, Moon Ju Kim, Barry Watson Krumm, Donald William McCauley, John Fenton Scanlon
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Patent number: 5649155Abstract: In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a line in said cache memory, the bin number and line position identification of the line in the cache memory are saved in a continuation register. Then, subsequently, when data is fetched from the same line, it is fetched by a continuation request wherein the data saved in the continuation register is used to access the cache memory. The continuation registers provide the abbreviated address data for comparison in both PSC (program store compare) and OSC (operand store compare).Type: GrantFiled: March 31, 1995Date of Patent: July 15, 1997Assignee: International Business Machines CorporationInventors: Barry Watson Krumm, Steven Tyler Comfort, Jin Ji, John Stephen Liptay, Charles Franklin Webb, David Man Chow Wong, Steven QiHong Ying
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Patent number: 5649140Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.Type: GrantFiled: March 31, 1995Date of Patent: July 15, 1997Assignee: International Business Machines CorporationInventors: Karl Jean Duvalsaint, Mark Steven Farrell, Barry Watson Krumm, Donald William McCauley, Charles Franklin Webb
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Patent number: 5391580Abstract: A biocompatable multi-layer article suitable for use in blood oxygenation is disclosed. The article is made up of a microporous polypropylene tube, a perm-selective, water vapor impermeable, carbon dioxide and oxygen permeable, homogeneous layer directly adhered to the polypropylene tube and active heparin linked through a covalent bond to the permselective layer. The polypropylene tube has an inside diameter from 240 to 400 .mu.m, a wall thickness from 10 to 50 .mu.m, and a porosity from 20 to 80 percent. The perm-selective layer is a polysulfone which has the structure ##STR1## where R is an alkyl group having 16 carbon atoms and n is 3,500 to 35,000. A method for producing a biocompatible multi-layer article suitable for use in blood oxygenation is also disclosed. The method involves the steps of immersing a microporous polypropylene tube which has an inside diameter from 240 to 400 .mu.m, a wall thickness from 10 to 50 .mu.Type: GrantFiled: May 10, 1993Date of Patent: February 21, 1995Assignee: Anatrace Inc.Inventors: Mary B. Douglas, Don N. Gray, Barry Watson, Christopher S. Youngen