Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access

Abstract: The application discloses a data processor operable to process data, said data processor comprising: a cache having a data item storage location identified by an address; a hash value generator operable to generate a hash value from at least some of said bits of said address said hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to a plurality of storage locations within said cache; wherein in response to a request to access said data item storage location said data processor is operable to compare a hash value generated from said address with at least some of said plurality of hash values stored within said buffer. The comparison providing an indication of the storage location of the data item.

Abstract: A data processor operable to process data said data processor being operable to perform a plurality of processes or a plurality of applications on said data, said data processor comprising: a cache; a data storage unit operable to store a process or application identifier defining a process or application that is currently executing on said data processor on said data; wherein a data item storage location within said cache is indicated by an address, and said data processor further comprises: a hash value generator operable to generate a hash value from at least some of said bits of said address and at least some bits of said process or application identifier, said hash value having fewer bits than said address.

Abstract: Techniques for improving the performance of a data processing apparatus are disclosed. The data processing apparatus is operable to execute a data access instruction which causes a first plurality of data items to be transferred between registers and memory. The data processing apparatus is also operable to transfer a second plurality of data items between the registers and the memory in each processing cycle. The data processing apparatus comprises: decode logic operable in response to receipt of one of the data access instruction to determine a number of reserved processing cycles to be reserved for the execution of the data access instruction, the number of reserved processing cycles being determined to be a number of processing cycles which would enable greater than the first plurality of data items to be transferred in those reserved processing cycles. Hence, a greater number of processing cycles are reserved than are strictly necessary.