Abstract: A new front-end module is disclosed. In an embodiment the front-end module is configured to operate carrier aggregation modes using a cascade of switches and an intelligent set of bands. The module can be assembled by sub-modules.

Abstract: A new front-end module is disclosed. In an embodiment the front-end module is configured to operate carrier aggregation modes using a cascade of switches and an intelligent set of bands. The module can be assembled by sub-modules.

Abstract: A coupler comprises a first line and a second line which is broadside coupled to the first line in a first and a second section. The capacitance between the first and the second line per length unit of the first line is larger in the first section in comparison to the second section. The first and the second line form a first turn.

Abstract: An impedance circuit includes an input terminal, a first and a second capacitive arrangement and an output terminal coupled to the input terminal by a network. The network includes the first and the second capacitive arrangement. The first capacitive arrangement includes a varactor circuit having a varactor and at least one series circuit. The at least one series circuit includes a capacitor and a switch in series connection and is coupled parallel to the varactor circuit. The second capacitive arrangement comprises an additional capacitor.

Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.

Abstract: An amplifier circuit (10) comprises a driver stage (11) with a driver output (13). Moreover, the amplifier circuit (10) comprises a sensor (12). The sensor (12) comprises a variable attenuator (15) with a control input (16) for receiving a mode signal (SMODE). A sensor output (14) of the sensor (12) is coupled to the driver output (13) via the variable attenuator (15). A sensor signal (SE_RFOUT) is provided at the sensor output (14).

Abstract: Circuit unit (CU) comprising a heterojunction bipolar transistor and a long-gate pseudomorphic high-electron-mobility transistor. Either a source (S) or a drain (D) of the long-gate pseudomorphic high-electron-mobility transistor is electrically coupled with either a collector (C) or an emitter (E) of the heterojunction bipolar transistor.

Abstract: An amplifier circuit (10) comprises a driver stage (11) with a driver output (13). Moreover, the amplifier circuit (10) comprises a sensor (12). The sensor (12) comprises a variable attenuator (15) with a control input (16) for receiving a mode signal (SMODE). A sensor output (14) of the sensor (12) is coupled to the driver output (13) via the variable attenuator (15). A sensor signal (SE_RFOUT) is provided at the sensor output (14).

Abstract: A coupler comprises a first line (31) and a second line (32) which is broadside coupled to the first line (31) in a first and a second section (42, 53). The capacitance between the first and the second line (31, 32) per length unit of the first line (31) is larger in the first section (42) in comparison to the second section (53). The first and the second line (31, 32) form a first turn (40).

Abstract: An impedance circuit includes an input terminal, a first and a second capacitive arrangement and an output terminal coupled to the input terminal by a network. The network includes the first and the second capacitive arrangement. The first capacitive arrangement includes a varactor circuit having a varactor and at least one series circuit. The at least one series circuit includes a capacitor and a switch in series connection and is coupled parallel to the varactor circuit. The second capacitive arrangement comprises an additional capacitor.

Abstract: A peak voltage protection circuit for protecting an associated High Voltage NPN transistor (T3) against breakdown, the protection circuit comprising a Low Voltage NPN element (T15) for sensing a sensor voltage related to a base-collector voltage of the associated High Voltage NPN transistor (T3). The circuit further comprises an activation circuit for limiting the base-collector voltage of the associated High Voltage NPN transistor (T3) upon triggering. The Low Voltage NPN element (15) is coupled to the activation circuit for triggering it upon the sensor voltage exceeding a breakdown voltage of the Low Voltage NPN transistor (T15).

Abstract: A phase locked loop has a voltage controlled oscillator with two tuning inputs. One tuning input can be supplied with a feedback signal via a frequency divider in a conventional phase locked loop. A frequency word, which is provided anyway for the purpose of setting the division ratio of the PLL and hence for the purpose of frequency preselection, is used not only to supply the frequency divider but also for compensatory tuning of frequency-determining components in the oscillator. The phase locked loop allows, particularly in inexpensive open loop modulation methods, a significant reduction in the frequency drift by virtue of a smaller or disappearing discrepancy in the tuning voltage in conjunction with a reduction in the memory effect of capacitors in loop filters using particularly simple circuitry measures.

Abstract: A phase locked loop has a voltage controlled oscillator with two tuning inputs. One tuning input can be supplied with a feedback signal via a frequency divider in a conventional phase locked loop. A frequency word, which is provided anyway for the purpose of setting the division ratio of the PLL and hence for the purpose of frequency preselection, is used not only to supply the frequency divider but also for compensatory tuning of frequency-determining components in the oscillator. The phase locked loop allows, particularly in inexpensive open loop modulation methods, a significant reduction in the frequency drift by virtue of a smaller or disappearing discrepancy in the tuning voltage in conjunction with a reduction in the memory effect of capacitors in loop filters using particularly simple circuitry measures.