Patents by Inventor Bart Becnel

Bart Becnel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12580916
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to, in response to receiving an architecture roadmap comprising one or more operational tasks, execute the machine learning algorithm to evaluate the operational tasks associated with the architecture roadmap, determine one or more reviewing guidelines based on the operational tasks, determine a reviewing entity profile of the one or more reviewing entity profiles comprising a reviewing parameter that at least partially match a reviewing guideline of the reviewing guidelines, determine a reviewing entity associated with the reviewing entity profile, and assign the operational tasks to the reviewing entity. The processor is configured generate one or more access commands configured to facilitate access to a one or more resources and transmit the access commands to the reviewing entity. The resources allow the operational tasks to be evaluated by the reviewing entity.
    Type: Grant
    Filed: June 18, 2024
    Date of Patent: March 17, 2026
    Assignee: Boost SubscriberCo L.L.C.
    Inventors: Sandeep N. Sadhwani, Bart Becnel
  • Publication number: 20250383939
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to, in response to receiving an order to generate a request, execute a machine learning algorithm to evaluate one or more input fields associated with a response in accordance with one or more machine learning models and determine one or more evaluation domains based on the input fields. The processor is configured to determine a first priority order relating to first operational tasks, determine a second priority order relating to second operational tasks, generate an architecture roadmap comprising the first operational tasks and the second operational tasks, and transmit the architecture roadmap to one or more reviewing entities. The first priority order is greater than the second priority order. The architecture roadmap is a plan to perform the first operational tasks and the second operational tasks over a time period.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 18, 2025
    Inventors: Sandeep N. Sadhwani, Bart Becnel
  • Publication number: 20250383913
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to, in response to receiving an architecture roadmap comprising one or more operational tasks, execute the machine learning algorithm to evaluate the operational tasks associated with the architecture roadmap in accordance with one or more machine learning models, and assign the operational tasks to an evaluation group comprising one or more reviewing entities. The processor is configured to receive a status update from the evaluation group. The status update indicates whether the operational tasks are performed within the time period. The processor is configured to determine whether the operational tasks are performed within the time period, generate a report referencing that the evaluation group completed the operational tasks in response to determining that the operational tasks are performed within the time period, and transmit the report to a data aggregator.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 18, 2025
    Inventors: Sandeep N. Sadhwani, Bart Becnel
  • Publication number: 20250385914
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to, in response to receiving an architecture roadmap comprising one or more operational tasks, execute the machine learning algorithm to evaluate the operational tasks associated with the architecture roadmap, determine one or more reviewing guidelines based on the operational tasks, determine a reviewing entity profile of the one or more reviewing entity profiles comprising a reviewing parameter that at least partially match a reviewing guideline of the reviewing guidelines, determine a reviewing entity associated with the reviewing entity profile, and assign the operational tasks to the reviewing entity. The processor is configured generate one or more access commands configured to facilitate access to a one or more resources and transmit the access commands to the reviewing entity. The resources allow the operational tasks to be evaluated by the reviewing entity.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 18, 2025
    Inventors: Sandeep N. Sadhwani, Bart Becnel
  • Publication number: 20250384338
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The processor is configured to, in response to receiving an order to generate a request, execute a machine learning algorithm to evaluate one or more guidelines associated with the request in accordance with one or more machine learning models and determine one or more knowledge areas based on the guidelines. Further, the processor is configured to determine first entry fields relating to a first knowledge area of a knowledge areas and determine second entry fields relating to a second knowledge area of a knowledge areas. The processor is configured to generate the request comprising the first entry fields and the second fields and transmit the request to a data aggregator configured to compile the information associated with the communication device type.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 18, 2025
    Inventors: Sandeep N. Sadhwani, Bart Becnel