Abstract: An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. Column readout circuitry coupled to the image sensor pixel via a column line. The image sensor pixel may have a pixel output path that is capacitive coupled to the column line via a capacitor. An input terminal of the capacitor at the image sensor pixel may be coupled to a pre-charging transistor. The pre-charging transistor may connect the input terminal of the capacitor to a grounding voltage. During readout operations, the pre-charging transistor may be activated before a row select transistor is activated to read out reset or image level signals. By capacitively coupling the image sensor pixel to the column line, pixel signal readout operations such as signal readout speed may be improved while pixel power may be reduced.

Abstract: An image sensor may include an array of image sensor pixels. Each image sensor pixel in the array may be a global shutter pixel that includes first transistors and second transistors that are substantially larger than the first transistors. The second transistors may receive row control signals from peripheral row drivers formed at the edge of the array. Each pixel may further include local driver circuits interposed between the peripheral row drivers and the second transistors. Each local driver circuit may include a pull-down transistor for driving a row control signal low and a pull-up transistor for driving the row control signal high. Each local driver may optionally be shared among two or more adjacent pixels in a given row. The local drivers help reduce the total capacitive loading at the output of the peripheral row drivers and can therefore help improve row driver performance and minimize integration time.

Abstract: An image sensor may include an array of image sensor pixels. Each image sensor pixel in the array may be a global shutter pixel that includes first transistors and second transistors that are substantially larger than the first transistors. The second transistors may receive row control signals from peripheral row drivers formed at the edge of the array. Each pixel may further include local driver circuits interposed between the peripheral row drivers and the second transistors. Each local driver circuit may include a pull-down transistor for driving a row control signal low and a pull-up transistor for driving the row control signal high. Each local driver may optionally be shared among two or more adjacent pixels in a given row. The local drivers help reduce the total capacitive loading at the output of the peripheral row drivers and can therefore help improve row driver performance and minimize integration time.

Abstract: An image sensor pixel may include a photodiode, a floating diffusion, and a transfer gate. Column readout circuitry coupled to the image sensor pixel via a column line. The image sensor pixel may have a pixel output path that is capacitive coupled to the column line via a capacitor. An input terminal of the capacitor at the image sensor pixel may be coupled to a pre-charging transistor. The pre-charging transistor may connect the input terminal of the capacitor to a grounding voltage. During readout operations, the pre-charging transistor may be activated before a row select transistor is activated to read out reset or image level signals. By capacitively coupling the image sensor pixel to the column line, pixel signal readout operations such as signal readout speed may be improved while pixel power may be reduced.

Abstract: An image sensor may contain an array of imaging pixels arranged in rows and columns. To support lower speed operation while minimizing power consumption, the image sensor may alternate between a high power context and a low power context. When transitioning between the high power and low power contexts, an in-rush current limiting circuit may be used to slowly ramp up or ramp down the bias current to help minimize power supply voltage rippling. The in-rush current limiting circuit may be digitally controlled using a current ramping digital-to-analog converter, may implement linear current ramping, or may implement a current feedback ramping scheme.

Abstract: Image sensors may include an array of image sensor pixels. A subset of the array, sometimes referred to as a region of interest (“ROI”), can be read out using vertical readout lines and diagonal readout lines. The diagonal readout lines enable multiple adjacent or nonadjacent rows in the ROI to be simultaneously read out. Configured and operated in this way, frame rate gains can be achieved by reducing the ROI size in both the Y direction and the X direction.

Abstract: An imaging system may include an image sensor having an array of dual gain pixels. Each pixel may be operated using an improved three read method and an improved four read method such that all signals are read in a high gain configuration in order to prevent electrical offset in signal levels. Each pixel may be operated using an improved three read, two analog to digital conversion (ADC) method in which a frame buffer is used to store calibration data. Each pixel may be operated using an improved three read, three ADC method in which no frame buffer is required. A high dynamic range image signal may be produced for each pixel based on signals read from the pixel and on light conditions.

Abstract: An imaging system may include an image sensor having an array of dual gain pixels. Each pixel may be operated using a two read method such that all signals are read in a high gain configuration in order to improve the speed or to reduce the power consumption of imaging operations. Each pixel may be operated using a two read, two analog-to-digital conversion method in which two sets of calibration data are stored. A high dynamic range (HDR) image signal may be produced for each pixel based on signals read from the pixel and on light conditions. The HDR image may be produced based on a combination of high and low gain signals and one or both of the two sets of calibration data. A system of equations may be used for generating the HDR image. The system of equations may include functions of light intensity.

Abstract: An imaging system may include an image sensor having an array of dual gain pixels. Each pixel may be operated using an improved three read method and an improved four read method such that all signals are read in a high gain configuration in order to prevent electrical offset in signal levels. Each pixel may be operated using an improved three read, two analog to digital conversion (ADC) method in which a frame buffer is used to store calibration data. Each pixel may be operated using an improved three read, three ADC method in which no frame buffer is required. A high dynamic range image signal may be produced for each pixel based on signals read from the pixel and on light conditions.

Abstract: An imaging system may include an image sensor having an array of dual gain pixels. Each pixel may be operated using a two read method such that all signals are read in a high gain configuration in order to improve the speed or to reduce the power consumption of imaging operations. Each pixel may be operated using a two read, two analog-to-digital conversion method in which two sets of calibration data are stored. A high dynamic range (HDR) image signal may be produced for each pixel based on signals read from the pixel and on light conditions. The HDR image may be produced based on a combination of high and low gain signals and one or both of the two sets of calibration data. A system of equations may be used for generating the HDR image. The system of equations may include functions of light intensity.

Abstract: An in-pixel correlated double sampling (CDS) pixel and methods of operating the same are provided. The CDS pixel includes a photodetector to accumulate radiation induced charges, a floating diffusion element electrically coupled to an output of the photodetector through a transfer switch, and. a capacitor-element having an input node electrically coupled to an amplifier and through the amplifier to the floating diffusion element and an output node electrically coupled to an output of the pixel. The capacitor-element is configured to sample a reset value of the floating diffusion element during a reset sampling and to sample a signal value of the floating diffusion element during a signal sampling.