Patents by Inventor Bart Degroote

Bart Degroote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Etching of structures with high topography
    Patent number: 7393768
    Abstract: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: July 1, 2008
    Assignee: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventor: Bart Degroote
  • Recursive spacer defined patterning
    Publication number: 20070065990
    Abstract: A method for the patterning of a plurality of fins in a MugFET device is provided. The method involves depositing at least one temporary pattern using photolithography. Further processing steps include a combination of depositing a conformal layer and spacer defined patterning of the conformal layer such that a very high density of fins can be achieved. The distance between the fins is no longer determined by photolithography, which is only used to define the temporary pattern which is removed in further processing, but instead by the thickness of the conformal layer, with all fins defined by spacers. Additionally an improved line edge roughness is achieved for the fins using the method.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 22, 2007
    Inventors: Bart Degroote, Rita Rooyackers
  • Etching of structures with high topography
    Publication number: 20060110928
    Abstract: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.
    Type: Application
    Filed: September 14, 2005
    Publication date: May 25, 2006
    Inventor: Bart Degroote