Abstract: A packetizer arrangement is disclosed with at least one packetizer device (PDPI1..PDPIM, PDPO1..PDPOM) for generating packets of respective individual packet streams from corresponding respective individual data streams (IDS1..IDSN) which are multiplexed and form part of an incoming data stream (CDS). Each of the packets includes a set of subsequent data portions of a corresponding respective individual data stream, and a last data portion included in the set is the one incoming substantially a time interval after a packet immediately preceding the present packet has been generated, this time interval corresponding to the length of this packet.

Abstract: An asynchronous switching node is described for distributing cells from an input port (I1, . . . , IN) of a node (ND) to a group of output ports (LG1, . . . , Lgk) thereof. The asynchronous switching node includes switching stages (S1, S2, S3) each having a switching element (S11, . . . , S3N) with inlets (IP1-IPN) and outlets (OP1-OPN). Each switching element (S11, . . . , S3N) has a routing logic circuit (MC1; MC2; RL) for routing one of the cells from one of the inlets (IP1-IPN) of one of the switching element (S11, . . . , S3N) to one of the outlets (OP1-OPN) thereof based on an internal routing label (LGA; SRT) associated with a cell. The switching element (S11, . . . , S3N) uses the internal routing label (LGA; SRT) to identify at least one distribution tree having branches (BR1, . . . , BR6 ) which connect the input port (I1, . . . , IN) with the group of output ports (LG1, . . . , Lgk).

Abstract: A cell resequencing system is provided for a resequencing section (RS) of a telecommunication network through which cells of communications are transmitted. The resequencing section includes cell switching networks (SN2) having inlets (I2l/I2n/I2N) coupled to inputs (S1l/S1n/S1N) and outlets (N2l/N2m/N2M). The cells are subjected to a first variable time delay. The cell resequencing system (C1l/C1n/C1N, CK1; R2l/R2m/R2M, CK2) includes latches (R2l/R2m/R2M) coupled between the outlets (N2l/N2m/N2M) and the outputs (S2l/S2m/S2M) to subject the cells to a second variable time delay chosen for each cell so the sum of the first and second variable time delay is substantially equal to a predetermined constant time value, which determines the size of the latches (R2l/R2m/R2M). The resequencing section (RS) has two inputs (S1l, S1n/S1N) each coupled to a distinct inlet (I2l/I2n/I2 N) via a distinct transmission link (TLl/TLn/TLN).

Abstract: A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each initial address (AI) at least one bit (C1) with a fixed rank; forms (1) an address called the selection address (AS) from each bit or bits (C1); extracts from each initial address (AI) a series of bits (C3, C6) using a format (M1i) selected from multiple predetermined first formats (M11, M12, M13, M14), as a function of the selection address; forms (2) with this series of bits (C3, C6) a binary word called the first relative address (AV1); and adds this first relative address to an address called the predetermined basic address (AB(M1i)) associated with the format (M1i) selected to determine this first relative address so as to obtain an address called the first reduced address (AT1) having a smaller number of bits than the initial address (AI); and wherein the basic address (AB(M1 i)) associated with the one (M1i) in the

Abstract: The packet transfer control arrangement ensures that an information packet transferred from an input to an output of a packet switching network is available in correct form at that output. It includes copying means (SE11/SEmn) located at the input of the network to make copies of the packet to be transferred, routing means (HA11/HAmn; SE11/SEmn) to transfer these copies independently from each other and possibly over at least partly distinct paths from an input to an output of the network and filtering modules (F11/Fmn) to filter out one of the copies at the output of the network.

Abstract: A communication system includes a main station (MS) and a plurality of substations (SX/SZ) which include each a transceiver and are all connected in parallel to first (UL) and second (DL) unidirectional links on which recurrent first and second cells of fixed length are transmitted in opposite direction. Each of these cells contains a plurality of signalling channels smaller than the number of substations. When a substation has to transmit data it starts an allocation procedure wherein the substation cooperates with the main station and by which a channel is allocated to it. Afterwards prior to transmitting the data the substation transmits a request signal in the allocated channel and starts transmission after having received from the main station a grant signal in the homologous signalling channel of a second cell. De-allocation of a channel occurs as soon as the latter is no longer needed.

Abstract: A telecommunication system for transmitting cells through switching nodes (N1-3) interconnected by groups (LG12, LG23) of transmission links, each node including an asynchronous switching network (SN1-3) which comprises several switch elements. At least one of these switch elements possesses a routing group possibility whereby the cells are distributed over its outlets and so further over the different transmission links of the link group to which the switching network is connected. This distribution is performed in function of a self-routing tag which is derived from external routing data associated with the cell. At the input ports of either each or only the first switching network (SN1) of the system, the external routing data is translated in a self-routing tag which is for instance added to the header of the cell, while at the output ports of each or of only the last switching network (SN3) of the system respectively, the self-routing tag is removed from this header.

Abstract: Communication switching element to switch M signal inputs (I(1) to I(M) to any of N signal outputs (O(1) to O(N)) and comprising MN buffers (Q(11) to Q(MN) which are arranged in a matrix of M rows and N columns. Each buffer is used to store cells during their transit from the associated input to the associated output.