Abstract: The disclosed signal strength adapter circuit includes a signal adapter (20) having a signal input (21) for receiving a signal whose strength is to be adapted, a digital set input (22) for receiving a strength value, and a signal output (23) for producing an adapted signal whose strength corresponds to the strength value on the set input (23). At successive discrete instants, a generator (24) generates a series of function values which determine an exponential time function (30) in coarse steps. The circuit includes an adapter circuit (26, 27) for adapting the signal strength in fine steps in the time intervals between the instants at which the function values are generated.

Abstract: A programmable logic unit performs only monadic, dyadic logic bit level, rather than arithmetic, operations in order to achieve high speed. The unit is formed of section for each output bit position. Each section includes a general function block which simultaneously performs as desired, one or more of the operations cntl1.A.B, cntl2.A.B, cntl3.A.B and cntl4.A.B, wherein A, A, B, B and cntl1 to cntl4 are logic signals and control signals respectively. The inputs of the general function block are connected to a data distribution bus via a multiplex circuit. This connection between the multiplex inputs and the distribution bus can be selected as desired (once), so that the number of different logic operations that can be selected is very large.