Abstract: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.

Abstract: An apparatus having an inter-domain electrostatic discharge (ESD) protection circuit for protection of an integrated circuit (IC) with multiple power domains. The protection circuit in response to an ESD event provides an ESD protection between different power domains. Specifically, the protection circuit comprises at least one clamp coupled to one power domain, which conducts current during an ESD event to provide extra current in the interface line between the two different power domains. This extra current also in turn increases the voltage over the impedance element on the interface line, thus improving the design margins for the ESD protection and providing a better ESD protection capability for IC products.

Abstract: The present invention provides an ESD protection circuit for a ESD clamp such as an SCR in the protection of an integrated circuit. In one embodiment of the invention, the SCR having at least one interspersed high-doped first region formed within a first lightly doped region and at least one interspersed high-doped second region formed within a second lightly doped region. The circuit further comprising at least one guardring connected to at least one trigger tap of the SCR to collect the ESD current to provide for a fast and easier triggering of the SCR.

Abstract: The present invention provides an improvement on ESD protection circuitry by controlling the trigger circuit to prevent the unwanted triggering of the device. The circuitry includes an ESD clamp with a trigger circuit coupled to the clamp. Both the clamp and the trigger circuit are coupled to a first reference potential. The circuitry also includes a control line coupled to the trigger circuit. The control line is coupled to a second reference potential to further control the behavior of the trigger circuit such that when the power is supplied to the second reference potential, the control line disables the trigger circuit, and when power is not supplied to the second reference potential, the control line enables the trigger circuit.

Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Abstract: The present invention provides an integrated circuit for improved ESD protection and method of forming the same. The integrated circuit comprises a substrate and an insulating layer formed over the substrate. The circuit also comprises a field effect field effect transistor (FET) formed over the insulating layer. The FET includes a well region of a first conductivity type. The circuit also includes a well resistor coupled to the FET to provide ballasting to the circuit. The well resistor includes a well region also of the first conductivity type.

Abstract: Apparatus for ESD circuit protection including a trigger subcircuit coupled between a first voltage reference potential and second voltage reference potential and an ESD shunt subcircuit coupled to the trigger subcircuit between a circuit device to be ESD-protected and the second voltage reference potential. The ESD shunt subcircuit is adapted for connection by a pad of an integrated circuit (IC) connection. The ESD shunt subcircuit is a silicon-controlled rectifier (SCR) that has an anode connected to the circuit device to be ESD-protected and a cathode connected to the second voltage reference potential. The trigger subcircuit is either an RC-triggered PMOS or a GGNMOS and series connected resistor.

Abstract: A method and apparatus for providing ESD protection. An ESD clamp is connected across the terminals to be protected circuit. The clamp is coupled to a current detector that activates the clamp when current from an ESD event exceeds a predefined limit.

Abstract: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.

Abstract: An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.

Abstract: A method and apparatus for providing ESD protection. An ESD clamp is connected across the terminals to be protected circuit. The clamp is coupled to a current detector that activates the clamp when current from an ESD event exceeds a predefined limit.

Abstract: A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Abstract: An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.