Abstract: A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter. The coefficient improvement module is configured to update the coefficients in the lookup table.

Abstract: A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filer. The coefficient improvement module is configured to update the coefficients in the lookup table.

Abstract: A system for receiving signals transmitted via serial links includes an analog-to-digital converter configured to sample the first analog signal at a first rate, and generate a first digital input signal having a second data rate. The system also includes a decimator coupled to an output of the equalizer and configured to downsample the first equalized signal to a decimated signal having the first data rate. The system further includes a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a second slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter.

Abstract: A system for receiving signals transmitted via serial links includes an analog-to-digital converter configured to sample the first analog signal at a first rate, and generate a first digital input signal having a second data rate. The system also includes a decimator coupled to an output of the equalizer and configured to downsample the first equalized signal to a decimated signal having the first data rate. The system further includes a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a second slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

Abstract: System and method of timing recovery using calibration logic to correct non-idealities related to phase interpolation. The calibration logic includes a Look-Up Table (LUT) preloaded with a set of expected output phases of the interpolator. During operation, an input phase signal is quantized and supplied to the calibration logic. In response, the LUT outputs a subset of preloaded values that are closest to the quantized phase signal. Each preloaded value in the subset is compared with the input phase signal to identify the one that is closest to the input phase signal. The index of the identified preloaded value is used to correct the input phase signal. Thus, the input to the phase interpolator is calibrated based on a preloaded value that is closest to the input phase signal which is regarded as the desired phase shift to be achieved by the phase interpolator.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. Upon a good Signal-to-Noise Ratio (SNR) being achieved, a selected set of the tap weights of the equalizer filter are frozen or set to smaller values, while others continue to adapt and the timing recovery loop continues the clock recovery process. Thereby, the adaptation of equalization can be adjusted to attenuate the equalization filter's effect on clock delay correction by limiting the adaptation time or speed relative to those of the entire timing recovery loop.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

Abstract: System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

Abstract: System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.